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MT8930CE Datasheet(PDF) 35 Page - Mitel Networks Corporation |
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MT8930CE Datasheet(HTML) 35 Page - Mitel Networks Corporation |
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35 / 42 page ![]() MT8930C 9-67 † Timing is over recommended temperature & power supply voltages ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Figure 24 - Intel Bus Interface Timing (Write Cycle) Figure 25 - Intel Bus Interface Timing (Read Cycle) AC Electrical Characteristics† - Intel Bus Interface Timing (Ref. Figure 24 & 25) Characteristics Sym Min Typ‡ Max Units Test Conditions 1 Chip select setup time tCSS 10 ns 2 Chip select hold time tCSH 25 ns 3 Address Latch pulse width tALW 50 ns 4 Address setup time tADS 20 ns 5 Address hold time tADH 20 ns 6 Data setup time - Write tDWS 35 ns 7 Data hold time - Write tDHW 20 ns 8 Data output delay - Read tDOD 240 ns 50 pF load 9 Data hold time - Read tDHR 25 90 ns 50 pF load 10 Write pulse width tWPW 60 ns 11 RD, WR delay tRWD 60 ns 12 Read pulse width tRPW 240 ns 13 Read setup time tRDS 20 ns CS ALE AD0-7 WR RD VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL Address Data in tCSS tCSH tALW tADS tADH tRWD tDHW tWPW tRDS tDWS CS ALE AD0-7 WR RD VIH VIL VIH VIL VI/OH VI/OL VIH VIL VIH VIL tCSH tALW tADS tADH tDOD tDHR tRDS tCSS tRWD tRPW Address Data out |
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