SM5849 datasheet(21/26 Pages) NPC

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SM5849AF

NIPPON PRECISION CIRCUITS—21

Filter Characteristic Selection

Conversion rates from 0.45 to 2.2 times are sup-

ported using the following 6 ﬁlter types.

The ratio between the output sample rate and input

sample rate is measured automatically and the most

suitable ﬁlter type for this ratio is selected automati-

cally.

When the selected fs conversion ratio and the actual

sample rate conversion ratio do not coincide, the fol-

lowing phenomenon occur.

System Reset (RSTN)

At power-ON, all device functions must be reset. The

device is reset by applying a LOW-level pulse on

RSTN. At system reset, the internal arithmetic opera-

tion, output timing counter and internal ﬂag register

operation are synchronized on the next LRCI rising

edge. Note that all ﬂags are set to their defaults (all

LOW).

A power-ON reset signal can be applied from an

external microcontroller. For systems where ICLK

and LRCI are stable at power ON, initialization can

be performed by connecting a 0.001µF capacitor

between RSTN and VSS. Otherwise, a capacitor

value should be chosen such that RSTN does not go

HIGH until after LRCI and ICLK have stabilized.

Through Mode (THRUN)

Synchronizing Internal Arithmetic Timing

The clock on LRCI should pass through 1 cycle for

every 384 (ICKSL = HIGH) or 256 (ICKSL = LOW)

ICLK clock cycles to maintain correct internal arith-

metic sequence. If the number of ICLK cycles is dif-

ferent, increases or decreases, or any jitter is present,

device operation could be affected.

There is a ﬁxed-value tolerance within which the

internal sequence and LRCI clock timing are not

adversely affected.

Whenever the allowable tolerance is exceeded, the

internal sequence start-up may be delayed or fail.

When this occurs, there is a possibility that a click

noise will be generated.

Table 13. fs ratio and ﬁlter selection

Filter

mode

fs ratio (fso/fsi)

Selects range

C o n version

frequency

(example)

1.0 to 2.2

≥ 0.969697

Up conver ter

0.91875

0.864865 to

0.969697

48.0 to 44.1kHz

0.72562

0.711111 to

0.864865

44.1 to 32.0kHz

0.66667

0.627451 to

0.711111

48 to 32kHz

0.50000

0.492308 to

0.627451

48 to 24kHz,

96 to 48kHz

0.459375

≤ 0.492308

48 to 22.05kHz,

96 to 44.1kHz

Table 14. Mismatch condition and response

Condition1

1. An output noise may be generated if the fs conversion ratio changes at

a rate greater 0.119%/sec.

Response

Actual sample rate conversion

ratio is low er than the selected

ﬁlter conversion ratio

The audio band high-pass

d evelops aliasing noise.

Actual sample rate conversion

ratio is higher than the selected

ﬁlter conversion ratio

The audio band high-pass is cut

off.

Table 15. Through mode function description

T H R U N

Mode

Description

L O W

Through mode

Direct connections are made: LRCI

to LRCO, BCKI to BCKO , and DI to

DOUT. DMUTE is valid.

HIGH

N o r mal mode

Sample rate conver ter operation

Table 16. ICLK and clock tolerance

ICKSL

Allow a b le clock variation

HIGH (384fs mode)

+8 to

−6 cycles

L O W (256fs mode)

+4 to

−3 cycles

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