SM5849AF

NIPPON PRECISION CIRCUITS—22

TIMING DIAGRAMS

Input Timing Examples (DI, BCKI, LRCI)

Audio data input timing (right-justified 16-bit word, IFM1 = L, IFM2 = L, IWL1 = L, IWL2 = L)

Audio data input timing (right-justified 24-bit word, IFM1 = L, IFM2 = L, IWL1 = H, IWL2 = H)

Audio data input timing (left-justified 20-bit word, IFM1 = H, IFM2 = L, IWL1 = H, IWL2 = L)

All data bits after the LSB (20th bit) are ignored. Note that more than 20 BCKI cycles are required.

Audio data input timing (IIS-format 24-bit word, IFM1 = H, IFM2 = H, IWL1 = L, IWL2 = H)

Audio data input timing (right-justified 24-bit word, LSB first,

IFM1 = H, IFM2 = H, IWL1 = L, IWL2 = H)

LRCI(fsi)

BCKI(48fsi)

DI

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

124 25

48

LSB

MSB

MSB

LSB

LRCI(fsi)

BCKI(48fsi)

DI

1

24

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

25

48

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

LSBMSB

MSB

LSB

LRCI(fsi)

BCKI(48fsi)

DI

1

24

20

19

18

17

16

15

14

13

12

11

10

9

25

48

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

20

19

18

17

16

15

14

13

12

11

10

9

LSB

MSB

MSB

LSB

LRCI(fsi)

BCKI(64fsi)

DI

1

32 33

8

7

6

5

4

3

2

1

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

MSB

LSB

64

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

MSB

LRCI(fsi)

BCKI(64fsi)

DI

1

32

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

33

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

MSB

LSB

LSB

MSB

64