MT90221AL datasheet(39/114 Pages) MITEL

39 / 114 page

MT90221

15 and the minimum value is 0 (in the case the PHY

port is not to be used). The size of the TX Link FIFO

is deﬁned on a per group using the TX IMA Control

registers.

The device will not accept a cell from the UTOPIA

Interface if the internal Cell Ram is full. Status bit 0 in

the General Status register is set to 1 to indicate the

’no free cell in TX Cell RAM’ condition. The status bit

can be cleared by overwriting it with 0.

The UTOPIA Input block has the option to verify the

HEC of the cell coming from the ATM layer. Four

different options are available and are selected by bit

1 and 0 of the UTOPIA Input Control register.

•

The ’00’ option is used to always accept a cell

from the ATM layer. The HEC is veriﬁed and if

wrong, the UTOPIA Input counter associated

with the UTOPIA port for cells with bad HEC is

incremented. The MT90221 will re-generate a

valid HEC based on the content of the 4-byte

header that was received.

•

The ’01’ option is used to verify the HEC of an

incoming cell. If the HEC value is wrong and if it

can be corrected (1 bit error), then the cell is

corrected and accepted as a good cell. The bad

HEC counter is not incremented if the HEC is

corrected. The bad HEC counter is incremented

if the HEC value cannot be corrected. In this

mode, the cell is always accepted. The

MT90221 will re-generate a valid HEC based on

the content of the 4-byte header that was

received.

•

The ’10’ option is used to verify the HEC on the

incoming cell and discard the cell if the HEC

value is wrong. The bad HEC counter is

incremented if a cell is discarded.

•

The ’11’ option is similar to mode ’01’ except

that if the HEC value cannot be corrected, then

the cell is discarded. If the HEC value is

corrected, the bad HEC counter is not

incremented.

5.2

ATM Output Port

The MT90221 supports a 53 byte cell stream via the

ATM output port. Cells received at the ATM output

port are stored in the RX UTOPIA FIFO before being

processed by the UTOPIA Interface. The output of

the UTOPIA Interface can be stopped by the ATM

Layer device by de-asserting the RxENB* signal.

The start of a cell is marked with the SOC signal,

which is active during the transmission of the ﬁrst

byte of a cell. The following 52 bytes are expected to

belong to the same cell.

The RX byte clock (RxClk) can be up to 25 MHz and

is checked against the system clock. If the incoming

byte clock frequency is lower than 1/128 of the

system clock, bit 3 of the General Status register

will be set. This bit is cleared by overwriting it with

0.The RxClk signal has to be synchronized with the

System Clock for the proper operation of the

MT90220. Typically, both frequencies are equal but

the RxClk frequency can be lower.

Overﬂow

conditions

the

UTOPIA

FIFO

associated with any of the 8 PHY RX Addresses

cause a status bit to be set in either the IRQ UTOPIA

UNI Overﬂow Status or IRQ IMA Group Overﬂow

Status register. These status bits are cleared by

overwriting them with 0. Additionally, for each status

bit there is an Interrupt Enable bit in the associated

RX UTOPIA Link FIFO Overﬂow Enable or RX

UTOPIA

IMA

Group

FIFO

Overﬂow

Enable

an Interrupt register. See 6.2 Interrupt Block for more

details.

The size of the RX UTOPIA FIFO is ﬁxed at two cells

for the UNI PHY Addresses and four cells for the IMA

Group PHY Addresses.

5.3

UTOPIA Operation With a Single PHY

A single ATM layer device with a UTOPIA L2 MPHY

port can be connected to the ATM input port of one

MT90221. Another ATM-Layer device using the

UTOPIA L2 MPHY input interface is used to receive

ATM cells from the MT90221.

The address pins should be set to the value

programmed by the management interface.

In this mode, the bit 6 and 5 of the Test 1 register are

not to be set to 1 for the proper operation of the RX

Utopia port.

5.4

UTOPIA Operation with Multiple PHY

When more than one MT90221 are connected to a

single ATM Layer device the single TxClav and

RxClav scheme is used. Direct Status Indication and

Multiplexed

Status

Polling

schemes

are

not

supported. The necessary polling is performed by

the ATM-Layer device.

The

UTOPIA

Interface

transmit

and

receive

addresses, provided by the ATM-Layer device, are

used to de-multiplex the ATM-cell stream to as many

eight

MT90221s.

The

maximum

available

bandwidth for four E1 lines served by each MT90221

device is 2 MBytes/s.

MT90221AL Datasheet(PDF) 39 Page - Mitel Networks Corporation

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