MT9092AP datasheet(2/42 Pages) MITEL

2 / 42 page

MT9092

7-4

Figure 2 - Pin Connections

Pin Description

Name

Description

1M+

Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier from the

handset microphone.

2NC

No Connect. No internal connection to this pin.

3VBias

Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers.

Connect 0.1 µF capacitor to VSSA.

4VRef

Reference voltage for codec (Output). Nominally [(VDD/2)-1.5] volts. Used internally.

Connect 0.1 µF capacitor to VSSA.

5IC

Internal Connection. Tie externally to VSS for normal operation.

PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).

7DSTi

ST-BUS Serial Stream (Input). 2048 kbit/s input stream composed of 32 eight bit channels;

the first four of which are used by the MT9092. Input level is TTL compatible.

8DSTo

ST-BUS Serial Stream (Output). 2048 kbit/s output stream composed of 32 eight bit

channels. The MT9092 sources digital signals during the appropriate channel, time coincident

with the channels used for DSTi.

9C4i

4096 kHz Clock (Input). CMOS level compatible.

F0i

Frame Pulse (Input). CMOS level compatible. This input is the frame synchronization pulse

for the 2048 kbit/s ST-BUS stream.

VSSD

Digital Ground . Nominally 0 volts.

IRQ

Interrupt Request (Open Drain Output). An active low output indicating an unmasked HDLC

interrupt event. Requires 1 k

Ω pull-up to V

DD.

SCLK

Serial Port Synchronous Clock (Input). Data clock for MCS-51 compatible microport. TTL

level compatible.

DSTi

DSTo

C4i

F0i

VSSD

IRQ

SCLK

DATA 2

DATA 1

SPKR+

SPKR-

HSPKR+

HSPKR-

VDD

S12

S11

S10

44 PIN PLCC

MT9092AP Datasheet(PDF) 2 Page - Mitel Networks Corporation

MT9092AP Datasheet(HTML) 2 Page - Mitel Networks Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL