5

SP5668

PHASE NOISE

The SP5668 has been designed to offer good phase noise

performance even when operated with a standard low profile

4MHz crystal and a high comparison frequency, e.g. 2MHz.

The typical phase noise performance measured in the

standard application is contained in Table 4. It has been

demonstrated that even higher levels of performance will be

achieved in a tuner application.

TEST MODES

The programmable divider output divided by two Fpd/2 and

the comparison frequency Fcomp, can be switched to ports P0

and P1 respectively.

The charge pump can be forced to either source or sink

current, and may be disabled to high impedance state.

The varactor DRIVE output can be disabled by the OS bit

within the data word, so switching the external transistor 'OFF'

and allowing an external voltage to be written to the varactor

line for tuner alignment purposes.

The test modes are described in Table 2.

Fig. 3 Data format and timing

R2

R1

R0

RATIO

Comparison Frequency with a 4MHz

external reference

0002

2MHz

0014

1MHz

0108

500kHz

0

1

1

16

250kHz

1

0

0

32

125kHz

1

0

1

64

62.5kHz

1

1

0

128

31.25kHz

1

1

1

256

15.625kHz

Table 1 Reference division ratio

P1

P0

T0

FUNCTIONAL DESCRIPTION

X

X

0

Normal operation

0

0

1

Charge pump sink. LOCK output = Lo Z

0

1

1

Charge pump source. LOCK output = Hi Z

1

0

1

Charge pump disable. LOCK output = Lo Z

1

1

1

Port P1 = Fcomp: Port 0 = Fpd/2

X = Don't care

Table 2 Test modes

CLOCK

ENABLE

DATA

FREQUENCY DATA

P2

P1

P0

TO OS CO R2

R1

R0 PE

LSB

t : Programmable divider ratio control bits

R2

R1

R0

,,

t : Reference divider ratio control bits (see Table 1)

P2, P1, P0

t : Port control bits

CO

t : Charge Pump current select (see Table 3)

OS

t : Drive output disable switch

T0

t : Test mode enable (see Table 2)

MSB

PE

:

÷2 Prescaler (Enable = 1, Disable = 0)