SM5879 datasheet(12/20 Pages) NPC

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SM5879AV

NIPPON PRECISION CIRCUITS—12

FUNCTIONAL DESCRIPTION

System Clock

Note that the input clock accuracy and jitter greatly

inﬂuence the AC analog characteristics.

The system clock can be controlled by a crystal oscil-

lator consisting of a crystal connected between XTI

and XTO and a built-in CMOS invertor or, alterna-

tively, an external system clock. Since the built-in

CMOS invertor has a feedback resistor, the external

system clock can be AC coupled to XTI. The system

clock is output from CKO.

System Reset (RSTN)

System reset for SM5879AV is performed by a built-

in power ON reset circuit.

At system reset, the internal arithmetic operation and

output timing counter are synchronized with the next

LCRI rising edge and thereby reset again for syn-

chronization with external elements.

Analog output is muted by this resetting, and muting

is cleared by the ninth LCRI rise (See Figure 1).

However, noise is generated due to the change in

PWM output during a timing reset. An external mute

circuit is necessary to prevent this noise.

Audio Data Input (DI, BCKI, LRCI)

The digital audio data is input on DI in MSB-ﬁrst, 2s-

complement, 16-bit serial format.

Serial data bits are read into the SIPO register (serial-

to-parallel converter register) on the rising edge of the

bit clock BCKI.

The bit clock frequency on BCKI should be between

32fs and 64fs.

Figure 2. System reset timing

LRCI

Power on Switch

Internal

Reset

Output Muted

Figure 3.

16bit

MSB

LSB

16bit

MSB

LSB

Rch

Lch

LRCI

BCKI

(MAX64fs)

1 / fs

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