CS5336 datasheet(9/34 Pages) CIRRUS

9 / 34 page

output each bit, except the MSB, which is clocked

out by the L/R edge. As shown in Figure 4, when

FSYNC is high, serial data bits are clocked imme-

diately following the L/R edge.

In SLAVE mode with FSYNC controlled, as

shown in Figure 5, when FSYNC is low, only the

MSB is clocked out after the L/R edge. With

FSYNC low, SCLK is ignored. When it is desired

to start clocking out data, bring FSYNC high

which enables SCLK to start clocking out data.

Bringing FSYNC low will stop the data being

clocked out. This feature is particularly useful to

position in time the data bits onto a common se-

rial bus.

The serial nature of the output data results in the

left and right data words being read at different

times. However, the words within an L/R cycle

represent simultaneously sampled analog inputs.

In all modes, additional bits are output after the

data bits: 3 tag bits and a left/right indicator. The

tag bits indicate a near-to-clipping input condition

for the data word to which the tag bits are at-

tached. Table 2 shows the relationship between

input level and the tag bit values. The serial bit

immediately following the

tag bits is 0 for the

left channel, and 1 for the right channel. The re-

maining bits before the next L/R edge will be 1’s

for the left channel and 0’s for the right channel.

Normally, the tag bits are separated from the

audio data by the digital signal processor. How-

ever, if the tag bits are interpreted as audio data,

their position below the LSB would result as a

very small dc offset.

In all modes, SCLK is shown for the CS5336 and

CS5338, where data bits are clocked out on rising

edges. SCLK is inverted for the CS5339.

Input

012

Input

FSYNC

Input

SCLK

L/ R

Left Audio Data

Tag Bits

Left Data

Right Audio Data

Tag Bits

Right Data

16 17 18 19

SDATA

Output

15 14

T2 T1 T0

Tag

***

Falling FSYNC stops SCLK from

clocking out SDATA

Rising FSYNC enables

SCLK to clock out SDATA

SCLK for CS5336/8.

SCLK inverted for CS5339

Figure 5. Data Output Timing - SLAVE Mode, FSYNC controlled

Table 2. Tag Bit Definition

Input Level

T2 T1 T0

1.375 x FS

1.250 x FS to 1.375 x FS

1.125 x FS to 1.250 x FS

1.000 x FS to 1.125 x FS

-1.006dB to 0.000dB

-3.060dB to -1.006dB

-6.000dB to -3.060dB

< -6.000dB

FS = Full Scale (0dB) Input

CS5336, CS5338, CS5339

DS23F1

3-47

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