CS5336 datasheet(11/34 Pages) CIRRUS

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greater than 10

µF, as stated in the "Power-Up

Considerations" section.

During the offset calibration cycle, the digital sec-

tion of the part measures and stores the value of

the calibration input of each channel in registers.

The calibration input value is subtracted from all

future outputs. The calibration input may be ob-

tained from either the analog input pins (AINL

and AINR) or the zero pins (ZEROL and

ZEROR) depending on the state of the ACAL pin.

With ACAL low, the analog input pin voltages are

measured, and with ACAL high, the zero pin volt-

ages are measured.

As shown in Figure 6, the DCAL output is high

during calibration, which takes 4096 L/R clock

cycles. If DCAL is connected to the ACAL input,

the calibration routine will measure the voltage on

ZEROR and ZEROL. These should be connected

directly to ground or through a network matched

to that present on the analog input pins. Internal

offsets of each channel will thus be measured and

subsequently subtracted.

Alternatively, ACAL may be permanently con-

nected low and DCAL utilized to control a

multiplexer which grounds the user’s front end.

In this case, the calibration routine will measure

and store not only the internal offsets but also

any offsets present in the front end input circuitry.

During calibration, the digital output of both

channels is forced to a 2’s complement zero. Sub-

traction of the calibration input from conversions

after calibration substantially reduces any

power on click that might otherwise be experi-

enced. A short delay of approximately 40 output

words will occur following calibration for the

digital filter to begin accurately tracking audio

band signals.

Power-up Considerations

Upon initial application of power to the supply

pins, the data in the calibration registers will be

indeterminate. A calibration cycle should always

be initiated after application of power to replace

potentially large values of data in these registers

with the correct values.

The modulators settle very quickly (a matter of

microseconds) after the analog section is powered

on, either through the application of power, or by

exiting the power-down mode. The voltage refer-

ence can take a much longer time to reach a final

value due to the presence of large external capaci-

tance on the VREF pin; allow approximately

5 ms/

µF. The calibration period is long enough to

allow the reference to settle for capacitor values of

up to 10

µF. If a larger capacitor is used, addi-

tional time between APD going low and DPD

going low should be allowed for VREF settling

before a calibration cycle is initiated.

Grounding and Power Supply Decoupling

As with any high resolution converter, the ADC

requires careful attention to power supply and

grounding arrangements if its potential perform-

ance is to be realized. Figure 1 shows the

recommended power arrangements, with VA+,

VA- and VL+ connected to a clean

± 5 V supply.

VD+, which powers the digital filter, may be run

from the system +5V logic supply, provided that

it is not excessively noisy (<

± 50 mV pk-to-pk).

Alternatively, VD+ may be powered from VA+ via

a ferrite bead. In this case, no additional devices

should be powered from VD+. Analog ground and

digital ground should be connected together near

to where the supplies are brought onto the printed

circuit board. Decoupling capacitors should be as

near to the ADC as possible, with the low value

ceramic capacitor being the nearest.

The printed circuit board layout should have sepa-

rate analog and digital regions and ground planes,

CS5336, CS5338, CS5339

DS23F1

3-49

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