6

Rev.1.3

11 -

The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a

small, high quality ceramic capacitor, i.e. 0.1μF, should be placed as close to the IC as possible. When using ce-

ramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive

voltage ripple at input. The input voltage ripple for low ESR capacitors can be estimated by:

ΔVin = [ Iload/(Cin × fs) ] × (Vout/Vin) × (1 − Vout/Vin)

Where Cin is the input capacitance value.

6. Output capacitor

The output capacitor is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic

capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The out-

put voltage ripple can be estimated by:

ΔVout = [ Vout/(fs × L) ] × (1 − Vout/Vin) × [ Resr + 1 / (8 × fs × Cout) ]

Where Cout is the output capacitance value and Resr is the equivalent series resistance (ESR) value of the out-

put capacitor.

In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance.

The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can

be estimated by:

In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency.

For simplification, the output ripple can be approximated to:

ΔVout = [ Vout/(fs × L) ] × (1 − Vout/Vin) × Resr

The characteristics of the output capacitor also affect the stability of the regulation system. ELM613DA can be

optimized for a wide range of capacitance and ESR values.

7. Compensation components

ELM613DA employs current mode control for easy compensation and fast transient response. The system sta-

bility and transient response are controlled through the COMP pin. COMP pin is the output of the internal trans-

conductance error amplifier. A series capacitor and resistor combination sets a pole-zero combination to control

the characteristics of the control system.

The DC gain of the voltage feedback loop is given by:

Avdc = Rload × Gcs × Aea × Vfb/Vout

Where Aea is the error amplifier voltage gain; Gcs is the current sense transconductance and Rload is the load

resistor value.

The system has two poles of importance. One is due to the compensation capacitor (C1) and the output resistor

of the error amplifier, and the other is due to the output capacitor and the load resistor. These poles are located

at:

fp1 = Gea / (2π × C1 × Aea), fp2 = 1 / (2π × Cout × Rload)

Where Gea is the error amplifier transconductance.

The system has one zero of importance, due to the compensation capacitor (C1) and the compensation resistor

(R3). This zero is located at:

fz1 = 1 / (2π × C1 × R3)

The system may have another zero of importance, if the output capacitor has a large capacitance and/or a high

ESR value. The zero, due to the ESR and capacitance of the output capacitor, is located at:

fesr = 1 / (2π × Cout × Resr)