LE25S40AMC

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9. Chip Erase

Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 14 Chip Erase" shows the

timing waveforms, and Figure 21 shows a chip erase flowchart. The chip erase command consists only of the first bus

cycle, and it is initiated by inputting (60h) or (C7h). After the command has been input, the internal erase operation

starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can

also be detected using status register RDY.

Figure 14. Chip Erase

10. Page Program

Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page

addresses: A18 to A8). Before initiating page program, the data on the page concerned must be erased using small

sector erase, sector erase, or chip erase. "Figure 15 Page Program" shows the page program timing waveforms, and

Figure 22 shows a page program flowchart. After the falling CS, edge, the command (02H) is input followed by the

24-bit addresses. Addresses A18 to A0 are valid. The program data is then loaded at each rising clock edge until the

rising CS edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes, the

256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program

operation is not performed at the rising CS edge occurring at any other timing.

Figure 15. Page Program

SCK

SI

High Impedance

SO

CS

tCHE

Self-timed

Erase Cycle

60h / C7h

0

1

2

3

4

5

6

7

Mode3

Mode0

8CLK

MSB

tPP

Self-timed

Program Cycle

SCK

SI

High Impedance

SO

CS

PD

Add.

Add.

02h

Add.

PD

15

0

1

2

3

4

5

6

7

8

23

16

24

31 32

39 40

47

Mode3

Mode0

8CLK

PD

2079

MSB