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TDC-GP30 Datasheet(PDF) 74 Page - ams AG

Part # TDC-GP30
Description  Ultrasonic-Flow-Converter
PDF  89 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

TDC-GP30 Datasheet(HTML) 74 Page - ams AG

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TDC-GP30 Vol. 1
DB_GP30Y_Vol1_en.docx V0.0
www.acam.de
7-25
Bit
Description
Format
Reset
13:12
FWD1_MODE: Firmware Data 1 Mode
00:
No Change of FWD1_MODE state
(WO)
01:
FWD1 Read disabled when GP30 will be protected
10:
FWD1 Read enabled when GP30 will be protected
11:
No Change of FWD1_MODE state
(WO)
RB
b01
11:10
BG_MODE: Bandgap Mode
00:
No Change of BG_MODE state
(WO)
01:
Bandgap controlled as configured
10:
Bandgap always on
11:
No Change of BG_MODE state
(WO)
RB
b01
9:8
HSO_MODE: High Speed Oscillator Mode
00:
No Change of HSO_MODE state
(WO)
01:
HSO controlled as configured
10:
HSO always on
11:
No Change of HSO_MODE state
(WO)
RB
b01
7:6
DBG_EN: Debug Enable
00:
No Change of DBG_EN state
(WO)
01:
Debug Mode disabled
10:
Debug Mode enabled
11:
No Change of DBG_EN state
(WO)
RB
b01
5:4
UART_CRC_MODE: UART CRC Mode
00:
No Change of UART_CRC_MODE state
(WO)
01:
UART_CRC_MODE default
10:
UART_CRC_MODE as configured
11:
No Change of DBG_EN state
(WO)
RB
b01
3:2
HS_CLK_SEL: High Speed Clock Select
00:
No Change of HS_CLK_SEL state
(WO)
01:
If 4 MHz clock source, has to be initially configured after reset
10:
If 8 MHz clock source
11:
No Change of HS_CLK_SEL state
(WO)
RB
b10
1:0
CFG_OK: GP30 Configuration OK
00:
No Change of CFG_OK state
(WO)
01:
GP30 not properly configured
10:
GP30 properly configured
11:
No Change of CFG_OK state
(WO)
RB
b01
7.4.14
SHR_FW_TRANS_EN (Firmware Transaction Enable)
0x0DF
Bit
Description
Format
Reset
31:0
FW_TRANS_EN: Firmware Transaction Enable
Code to enable transactions of firmware into NVRAMs: h50F5_B8CA
Write only register
Status of this register can be checked in FW_TRANS_EN in register
BIT32
hAF0A
_7435



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