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AP3776B Datasheet(PDF) 11 Page - Diodes Incorporated |
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AP3776B Datasheet(HTML) 11 Page - Diodes Incorporated |
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11 / 17 page ![]() AP3776B Document number: DS36737 Rev. 6 - 2 11 of 17 www.diodes.com December 2015 © Diodes Incorporated AP3776B Function Description (Cont.) Iomax VCS_L VCS_M VCS_H Light-load Medium-load High-load VCSREF Iomax fsw 24kHz 60kHz LL mode Figure 4. Multiple Segment Peak Current at CV Mode 3. The LL Mode Operating (Typical Application with APR343) At no load and light load, the AP3776B works in Low Light mode (LL mode) and the output voltage is detected by APR343. In order to achieve ultra low standby power in LL mode, the static current (ICC_NL) of the AP3776B is reduced from 280μA to 100μA. • The conditions of exiting LL mode---VCPC>65mV or tOFF<tDELAY+30μs • The conditions of entering LL mode---VCPC<33mV and tOFF≥tDELAY+30μs In LL mode, when the APR343 detects the output voltage is lower than its trigger voltage, the APR343 VDET pin emits a periodical pulse current. This pulse current will generate a pulse voltage on feedback winding through the transformer coupling. When the AP3776B detects this VPULSE (>100mV is valid), primary switch immediately turns on to provide one energy pulse to supply output terminal and primary VCC. To achieve low standby power, the lower switching frequency is necessary. But if the off time is too long, the VCC voltage will reduce to very low level. To avoid VCC being lower than VOPR(Min), a minimum switching frequency is specified by the APR343 (tDIS). If VOUT does not fall below trigger voltage during tDIS, APR343 VDET pin will emit the periodical pulse current and let the primary switch turn on. 4. Leading Edge Blanking When the power switch is turned on, a turn-on spike will occur on the sense-resistor. To avoid false-termination of the switching pulse, a 500ns leading-edge blanking (from power MOSFET on) is built in. During this blanking period, the current sense comparator is disabled and the gate driver can’t be switched off. 5. Adjustable Line Compensation Since there is a constant delay time from the CS pin voltage reaching the given VCS reference to the power MOSFET turning off, the real primary peak current value always has a gap with the ideal value. The gap value changes with different input line voltage, which is caused by different current rising slope, results in different system constant current value. In order to eliminate the constant current deviation due to line voltage, the adjustable line compensation is introduced to AP3776B design. By sensing the negative voltage of FB pin which is linear to the line voltage, a current (ILINE) proportional to line voltage flows out from the CS pin to the resistor RLINE, and create an adjustable compensation voltage to clear up the primary current gap, so that the excellent line regulation of output current will be achieved. indc p aux FB FB FB LINE LINE CS V N N R R R k R V 2 1 2 _ 700 1 4 . 0 |
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