SI516 datasheet(5/22 Pages) SILABS

5 / 22 page

Si516

Rev. 1.0

Table 2. Vc Control Voltage Input

VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Control Voltage Range

0.1 x VDD

VDD/2

0.9 x VDD

Control Voltage Tuning Slope

(10 to 90% VDD)

Ordering option

60, 90, 120, 150

ppm/V

Kv Variation

Kv_var

—

±10

Control Voltage Linearity

LVC

BSL

–5

±1

Modulation Bandwidth

—

kHz

Vc Input Impedance

ZVC

—100

—



Table 3. Output Clock Frequency Characteristics

VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Nominal Frequency

CMOS, Dual CMOS

0.1

—

212.5

MHz

LVDS/LVPECL/HCSL

0.1

—

250

MHz

Temperature Stability

TA = –40 to +85 oC

–20

—

+20

ppm

Aging

Frequency drift over 10-year life

—

±8.5

ppm

Minimum Absolute Pull Range

APR

Ordering option

±30, ±50,±80, ±100

ppm

Startup Time

TSU

Minimum VDD until output fre-

quency (FO) within specification

——

Disable Time

FO > 10 MHz

—

µs

FO < 10 MHz

—

µs

Enable Time

FO > 10 MHz

—

µs

FO < 10 MHz

—

µs

Settling Time after FS Change

tFRQ

——

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