SI516 datasheet(6/22 Pages) SILABS

6 / 22 page

Si516

Rev. 1.0

Table 4. Output Clock Levels and Symmetry

VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

CMOS Output Logic High

VOH

0.85 x VDD

——

CMOS Output Logic Low

VOL

—

0.15 x VDD

CMOS Output Logic High

Drive

IOH

3.3 V

–8

—

2.5 V

–6

—

CMOS Output Logic Low

Drive

IOL

3.3 V

—

2.5 V

—

CMOS Output Rise/Fall Time

(20 to 80% VDD)

TR/TF

0.1 to 125 MHz,

CL = 15 pF

—0.8

1.2

0.1 to 212.5 MHz,

CL = no load

—0.6

0.9

LVPECL/HCSL Output

Rise/Fall Time

(20 to 80% VDD)

TR/TF

——

565

LVDS Output Rise/Fall Time

(20 to 80% VDD)

TR/TF

——

800

LVPECL Output Common

Mode

VOC

 to VDD – 2 V,

single-ended

—VDD –

1.4 V

—V

LVPECL Output Swing

 to VDD – 2 V,

single-ended

0.55

0.8

0.90

VPPSE

LVDS Output Common Mode

VOC

100

 line-line,

VDD = 3.3/2.5 V

1.13

1.23

1.33

LVDS Output Swing

Single-ended 100



differential termination

0.25

0.38

0.42

VPPSE

HCSL Output Common Mode

VOC

to ground

0.35

0.38

0.42

HCSL Output Swing

Single-ended

0.58

0.73

0.85

VPPSE

Duty Cycle

SI516 Datasheet(PDF) 6 Page - Silicon Laboratories

SI516 Datasheet(HTML) 6 Page - Silicon Laboratories

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Datasheet Download

Link URL