SI554 datasheet(2/15 Pages) SILABS

2 / 15 page

Si554

Rev. 1.1

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Supply Voltage1

VDD

3.3 V option

2.97

3.3

3.63

2.5 V option

2.25

2.5

2.75

1.8 V option

1.71

1.8

1.89

Supply Current

IDD

Output enabled

LVPECL

CML

LVDS

CMOS

—

120

108

130

117

108

Tristate mode

—

Output Enable (OE)

and Frequency Select FS[1:0]2

VIH

0.75 x VDD

——

VIL

——

0.5

Operating Temperature Range

–40

—

ºC

Notes:

1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 10 for further details.

2. OE and FS[1:0] pins include a 17 k

 resistor to VDD.

Table 2. VC Control Voltage Input

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Control Voltage Tuning Slope1,2,3

10 to 90% of VDD

—33

135

180

356

—

ppm/V

Control Voltage Linearity4

LVC

BSL

–5

±1

Incremental

–10

±5

+10

Modulation Bandwidth

9.3

10.0

10.7

kHz

VC Input Impedance

ZVC

500

—



Nominal Control Voltage

VCNOM

@ fO

—VDD/2

—

Control Voltage Tuning Range

0VDD

Notes:

1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 10.

2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.

3. KV variation is ±10% of typical values.

4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope

determined with VC ranging from 10 to 90% of VDD.

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