Si554

Rev. 1.1

3

Table 3. CLK± Output Frequency Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

LVDS/CML/LVPECL

10

—

945

MHz

CMOS

10

—

160

MHz

–20

–50

–100

—

—

—

+20

+50

+100

ppm

APR

±12

—

±375

ppm

Aging

Frequency drift over first year.

—

—

±3

ppm

Frequency drift over 15 year life.

—

—

±10

——

10

ms

Settling Time After FS[1:0]

Change

Both FS[1] and FS[0] changing

simultaneously

——

20

ms

Notes:

1. See Section 3. "Ordering Information" on page 10 for further details.

2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

4. Selectable parameter specified by part number.

Table 4. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

mid-level

—

V

swing (diff)

1.1

—

1.9

swing (single-ended)

0.55

—

0.95

mid-level

1.125

1.20

1.275

V

swing (diff)

0.5

0.7

0.9

2.5/3.3 V option mid-level

—

—

V

1.8 V option mid-level

—

—

V

2.5/3.3 V option swing (diff)

1.10

1.50

1.90

1.8 V option swing (diff)

0.35

0.425

0.50

—

V

—

—

0.4

Rise/Fall time (20/80%)

LVPECL/LVDS/CML

—

—

350

ps

—

1

—

ns

Symmetry (duty cycle)

SYM

LVPECL:

(diff)

LVDS:

1.25 V (diff)

CMOS:

45

—

55

%

Notes:

1. 50

 to V