Data Sheet

AD9655

DIGITAL SPECIFICATIONS

AVDD = 1.8 V and DRVDD = 1.8 V, unless otherwise noted.

Table 5.

Temperature

Min

Typ

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Full

0.2

3.6

V p-p

Input Voltage Range

Full

AGND − 0.2

AVDD + 0.2

V

Input Common-Mode Voltage

Full

0.9

V

Input Resistance (Differential)

25°C

15

kΩ

Input Capacitance

25°C

4

pF

LOGIC INPUTS (SCLK/DFS)

Logic 1 Voltage

Full

1.2

AVDD + 0.2

V

Logic 0 Voltage

Full

0

0.8

V

Input Resistance

25°C

30

kΩ

Input Capacitance

25°C

2

pF

LOGIC INPUT (CSB)

Logic 1 Voltage

Full

1.2

AVDD + 0.2

V

Logic 0 Voltage

Full

0

0.8

V

Input Resistance

25°C

26

kΩ

Input Capacitance

25°C

2

pF

LOGIC INPUT (SDIO/PDWN)

Logic 1 Voltage

Full

1.2

AVDD + 0.2

V

Logic 0 Voltage

Full

0

0.8

V

Input Resistance

25°C

26

kΩ

Input Capacitance

25°C

5

pF

Full

1.79

V

Full

0.05

V

DIGITAL OUTPUTS (D0x±, D1x±), ANSI-644

Logic Compliance

LVDS

Full

±298

±350

±400

mV

Full

1.15

1.22

1.30

V

Output Coding (Default)

Twos complement

DIGITAL OUTPUTS (D0x±, D1x±), LOW POWER, REDUCED SIGNAL OPTION

Logic Compliance

LVDS

Full

±170

±200

±231

mV

Full

1.15

1.22

1.30

V

Output Coding (Default)

Twos complement

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2

Specified for LVDS and LVPECL only.

3

Specified for 13 SDIO/PDWN pins sharing the same connection.

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