ADS1262 datasheet(45/134 Pages) TAOS

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st Stage

Sinc

5 Filter

Decimation A

(24, 48, 64)

nd Stage

Sinc

N Filter

Decimation B

(2...5760)

38400 SPS

19200 SPS

14400 SPS

921.6 kHz

2.5 SPS...7200 SPS

fCLK: 7.3728 MHz

fCLK/8

fMOD: 921.6 kHz

Modulator

FIR

14400 SPS

20 SPS

Averager

Average

(2,4,8)

Decimation

(30)

Filter Output

FIR Filter Section

600 SPS

10 SPS

5 SPS

2.5 SPS

FILTER[2:0] bits 7:5 of MODE1

(register address = 04h)

DR[3:0] bits 3:0 of MODE2

(register address = 05h)

000 = sinc1

001 = sinc2

010 = sinc3

011 = sinc4

100 = FIR

0000 = 2.5 SPS

0001 = 5 SPS

0010 = 10 SPS

0011 = 16.6 SPS

0100 = 20 SPS

0101 = 50 SPS

0110 = 60 SPS

0111 = 100 SPS

1000 = 400 SPS

1001 = 1200 SPS

1010 = 2400 SPS

1011 = 4800 SPS

1100 = 7200 SPS

1101 = 14400 SPS

1110 = 19200 SPS

1111 = 38400 SPS

ADS1262, ADS1263

www.ti.com

SBAS661B – FEBRUARY 2015 – REVISED JULY 2015

9.3.9 ADC1 Modulator

The ADC1 modulator is an inherently stable, fourth-order, 2 + 2 pipelined

ΔΣ modulator. The modulator samples

the analog input voltage at a high sample rate (fMOD = fCLK / 8 = 921.6 kHz) and converts the analog input to a

ones density bit stream. The digital filter receives the ones density bit stream output, and then filters and

decimates the data to yield the final conversion result.

9.3.10 Digital Filter

The digital filter of ADC1 receives the modulator output data and produces a high-resolution conversion result.

The digital filter low-pass filters and decimates the modulator data (rate reduction), yielding the final data output.

By adjusting the type of filtering, tradeoffs are made between resolution, data rate, line cycle rejection, and

conversion latency.

The digital filter has two selectable modes: sin (x) / x (sinc) mode and finite impulse response (FIR) mode (see

Figure 80). The sinc mode provides data rates of 2.5 SPS though 38400 SPS with selectable sinc orders of 1

through 5. The FIR filter provides simultaneous rejection of 50-Hz and 60-Hz power-line frequencies with data

rates 2.5 SPS through 20 SPS with single-cycle settled conversions.

Figure 80. Digital Filter Block Diagram

9.3.10.1 Sinc Filter Mode

The sinc filter consists of two stages: a variable-decimation, fixed-order sinc5 filter, followed by a variable-

decimation, variable-order sinc filter. The first-stage filter is sinc5. The sinc5 stage filters and down-samples the

modulator data (fCLK / 8 = 921.6 kHz) to 38400 SPS, 19200 SPS, and 14400 SPS by decimating to 24, 48, and

64, respectively. These data rates bypass the second filter stage and as a result have a sinc5 frequency

response profile. The second filter stage receives the data from the first stage at 14400 SPS. The second stage

reduces the data rate to produce output data of 7200 SPS to 2.5 SPS. The second stage is a variable-order sinc

filter that is programmable.

The combined decimation ratio of the first and second stages determine the output data rate as follows: data rate

= 921.6 kHz / (A · B). The filter order of the second stage affects the 50-Hz and 60-Hz rejection together with

conversion latency. The high-order sinc filter yields the widest 50-Hz and 60-Hz response null widths, but

correspondingly increases the conversion latency. The sinc order is programmed by the FILTER[2:0] bits of

respectively) for each data rate. The data rate is programmed by the DR[3:0] bits of register MODE2.

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