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ADS1262 Datasheet(PDF) 46 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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ADS1262 Datasheet(HTML) 46 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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46 / 134 page  N CLK CLK CLK CLK f f 1 f 1 f f f 1 f f » ¼ º « ¬ ª u » ¼ º « ¬ ª u » ¼ º « ¬ ª u » ¼ º « ¬ ª u 512 sin B B 512 sin 8 sin A A 8 sin H H H 5 sinc sinc N 5 ADS1262, ADS1263 SBAS661B – FEBRUARY 2015 – REVISED JULY 2015 www.ti.com Table 8. Sinc Filter Mode Data Rates and Decimation Ratio DATA RATE DR[3:0] BITS OF FIRST-STAGE SECOND-STAGE (SPS)(1) REGISTER MODE2 DECIMATION RATIO A DECIMATION RATIO B 2.5 0000 64 5760 5 0001 64 2880 10 0010 64 1440 16.6 0011 64 864 20 0100 64 720 50 0101 64 288 60 0110 64 240 100 0111 64 144 400 1000 64 36 1200 1001 64 12 2400 1010 64 6 4800 1011 64 3 7200 1100 64 2 14400 1101 64 1 19200 1110 48 1 38400 1111 24 1 (1) fCLK = 7.3728 MHz. Data rate scales with fCLK 9.3.10.1.1 Sinc Filter Frequency Response The low-pass filtering effect of the sinc filter sets the overall frequency response of the ADC. The frequency response of data rates 14400 SPS, 19200 SPS and 38400 SPS is that of the first filter stage. The frequency response of data rates 2.5 SPS ranging to 7200 SPS is the product of the first and second stage individual frequency responses. The overall filter response is given in Equation 14: where • f = signal frequency • fCLK = ADC clock frequency • A = First-stage decimation ratio (see Table 8) • B = Second-stage decimation ratio (see Table 8) • N = Second-stage filter order where N = 1 (sinc1), 2 (sinc2), 3 (sinc3), or 4 (sinc4) (14) The digital filter attenuates out-of-band noise that is present in the signal, and noise within the PGA and ADC modulator. Adjusting the filter by changing the decimation ratio and sinc order changes the filter bandwidth. Tradeoffs are made between signal bandwidth, noise, and filter latency. 46 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS1262 ADS1263 |
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