CAP1126 datasheet(12/73 Pages) MICROCHIP

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CAP1126

DS00001623B-page 12

 2015 Microchip Technology Inc.

4.2.1

SMBUS START BIT

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the

SMBus Clock line is in a logic ‘1’ state.

4.2.2

SMBUS ADDRESS AND RD / WR BIT

The SMBus Address Byte consists of the 7-bit slave address followed by the RD / WR indicator bit. If this RD / WR bit

is a logic ‘0’, then the SMBus Host is writing data to the slave device. If this RD / WR bit is a logic ‘1’, then the SMBus

Host is reading data from the slave device.

See Table 4-1 for available SMBus addresses.

4.2.3

SMBUS DATA BYTES

All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.

4.2.4

SMBUS ACK AND NACK BITS

The SMBus slave will acknowledge all data bytes that it receives. This is done by the slave device pulling the SMBus

Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write proto-

cols.

The Host will NACK (not acknowledge) the last data byte to be received from the slave by holding the SMBus data line

high after the 8th data bit has been sent. For the Block Read protocol, the Host will ACK each data byte that it receives

except the last data byte.

4.2.5

SMBUS STOP BIT

The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the

SMBus clock line is in a logic ‘1’ state. When the CAP1126 detects an SMBus Stop bit and it has been communicating

with the SMBus protocol, it will reset its slave interface and prepare to receive further communications.

4.2.6

SMBUS TIMEOUT

The CAP1126 includes an SMBus timeout feature. Following a 30ms period of inactivity on the SMBus where the

SMCLK pin is held low, the device will timeout and reset the SMBus interface.

The timeout function defaults to disabled. It can be enabled by setting the TIMEOUT bit in the Configuration register

(see Section 6.6, "Configuration Registers").

4.2.7

SMBUS AND I2C COMPATIBILITY

The major differences between SMBus and I2C devices are highlighted here. For more information, refer to the SMBus

2.0 and I2C specifications. For information on using the CAP1126 in an I2C system, refer to AN 14.0 Dedicated Slave

Devices in I2C Systems.

FIGURE 4-1:

SMBus Timing Diagram

SMDATA

SMCLK

TLOW

TRISE

THIGH

TFALL

TBUF

THD:STA

S - Start Condition

P - Stop Condition

THD:DAT

TSU:DAT

TSU:STA

THD:STA

TSU:STO

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