CAP1133 datasheet(10/63 Pages) MICROCHIP

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CAP1133

DS00001625B-page 10

 2015 Microchip Technology Inc.

4.0

COMMUNICATIONS

4.1

Communications

The CAP1133 communicates using the SMBus or I2C protocol.

The supports the following protocols: Send Byte, Receive Byte, Read Byte, Write Byte, Read Block, and Write Block.

In addition, the device supports I2C formatting for block read and block write protocols.

4.2

System Management Bus

The CAP1133 communicates with a host controller, such as an SIO, through the SMBus. The SMBus is a two-wire serial

communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in

Figure 4-1. Stretching of the SMCLK signal is supported; however, the CAP1133 will not stretch the clock signal.

4.2.1

SMBUS START BIT

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the

SMBus Clock line is in a logic ‘1’ state.

4.2.2

SMBUS ADDRESS AND RD / WR BIT

The SMBus Address Byte consists of the 7-bit slave address followed by the RD / WR indicator bit. If this RD / WR bit

is a logic ‘0’, then the SMBus Host is writing data to the slave device. If this RD / WR bit is a logic ‘1’, then the SMBus

Host is reading data from the slave device.

The CAP1133 responds to SMBus address 0101_000(r/w).

4.2.3

SMBUS DATA BYTES

All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.

4.2.4

SMBUS ACK AND NACK BITS

The SMBus slave will acknowledge all data bytes that it receives. This is done by the slave device pulling the SMBus

Data line low after the 8th bit of each byte that is transmitted. This applies to both the Write Byte and Block Write proto-

cols.

The Host will NACK (not acknowledge) the last data byte to be received from the slave by holding the SMBus data line

high after the 8th data bit has been sent. For the Block Read protocol, the Host will ACK each data byte that it receives

except the last data byte.

FIGURE 4-1:

SMBus Timing Diagram

SMDATA

SMCLK

TLOW

TRISE

THIGH

TFALL

TBUF

THD:STA

S - Start Condition

P - Stop Condition

THD:DAT

TSU:DAT

TSU:STA

THD:STA

TSU:STO

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