ADS4449 datasheet(21/56 Pages) TI1

21 / 56 page

DAB0P, DAB0M or

OVRABP, OVRABM

CLKINP,

CLKINM

AINP,

AINM

Common

Mode

VCM

CLKOUTABP,

CLKOUTABM

DAB[13:1]P,

DAB[13:1]M

BINP,

BINM

CINP,

CINM

DINP,

DINM

Configuration Registers

CLKOUTCDP,

CLKOUTCDM

DCD[13:1]P,

DCD[13:1]M

Digital

Block

DCD0P, DCD0M or

OVRCDP, OVRCDM

Output

Formatter

DDR

LVDS

14-Bit

ADC

14-Bit

ADC

14-Bit

ADC

14-Bit

ADC

Digital

Block

ADS4449

www.ti.com

SBAS603A – APRIL 2013 – REVISED JANUARY 2016

8 Detailed Description

8.1 Overview

The ADS4449 belong to TI’s low-power family of quad-channel, 14-bit, analog-to-digital converters (ADCs). High

performance is maintained while power is reduced for power-sensitive applications. In addition to its low power

and high performance, the ADS4449 has a number of digital features and operating modes to enable design

flexibility.

At every falling edge of the input clock, the analog input signal for each channel is sampled simultaneously. The

sampled signal in each channel is converted by a pipeline of low-resolution stages. In each stage, the sampled-

and-held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference (residue) between

the stage input and quantized equivalent is gained and propagates to the next stage. At every clock, each

subsequent stage resolves the sampled input with greater accuracy. The digital outputs from all stages are

combined in a digital correction logic block and are digitally processed to create the final code, after a data

latency of 10 clock cycles. The digital output is available in a double data rate (DDR) low-voltage differential

signaling (LVDS) interface and is coded in binary twos complement format.

The ADS4449 can be configured with a serial programming interface (SPI), as described in the Serial Interface

section. In addition, the device has control terminals that control power-down.

8.2 Functional Block Diagram

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