FDC2114RGHT datasheet(43/60 Pages) TI1

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FDC2212, FDC2214, FDC2112, FDC2114

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SNOSCZ5A – JUNE 2015 – REVISED JUNE 2015

Typical Application (continued)

6. Use the default values for the ERROR_CONFIG register (address 0x19). By default, no interrupts are

enabled

7. Program the MUX_CONFIG register

(a) Set the AUTOSCAN_EN to b1 bit to enable sequential mode

(b) Set RR_SEQUENCE to b10 to enable data conversion on three channels (channel 0, channel 1, channel

exceeds the oscillation tank frequency.

(d) The combined value for the MUX_CONFIG register (address 0x1B) is 0xC20D

8. Finally, program the CONFIG register as follows:

(a) Set the ACTIVE_CHAN field to b00 to select channel 0.

(b) Set SLEEP_MODE_EN field to b0 to enable conversion.

(d) Set the REF_CLK_SRC field to b1 to use the external clock source.

(e) Set the other fields to their default values.

(f) The combined value for the CONFIG register (address 0x1A) is 0x1601.

We then read the conversion results for channel 0 to channel 2 every 10ms from register addresses 0x00 to

0x05.

Based on the example configuration above, the following register write sequence is recommended:

Table 47. Recommended Initial Register Configuration Values (Multi-channel Operation)

ADDRESS

VALUE

COMMENTS

0x08

0x8329

RCOUNT_CH0

Reference count calculated from timing requirements (100 SPS) and

resolution requirements

0x09

0x8329

RCOUNT_CH1

Reference count calculated from timing requirements (100 SPS) and

resolution requirements

0x0A

0x8329

RCOUNT_CH2

Reference count calculated from timing requirements (100 SPS) and

resolution requirements

0x10

0x000A

SETTLECOUNT_CH0

Minimum settling time for chosen sensor

0x11

0x000A

SETTLECOUNT_CH1

Minimum settling time for chosen sensor

0x12

0x000A

SETTLECOUNT_CH2

Minimum settling time for chosen sensor

0x14

0x2002

CLOCK_DIVIDER_CH0

CH0_FIN_DIVIDER = 1, CH0_FREF_DIVIDER = 2

0x15

0x2002

CLOCK_DIVIDER_CH1

CH1_FIN_DIVIDER = 1, CH1_FREF_DIVIDER = 2

0x16

0x2002

CLOCK_DIVIDER_CH2

CH1_FIN_DIVIDER = 1, CH1_FREF_DIVIDER = 2

0x19

0x0000

ERROR_CONFIG

Can be changed from default to report status and error conditions

0x1B

0xC20D

MUX_CONFIG

Enable Ch 0 , Ch 1, and Ch 2 (sequential mode), set Input deglitch

bandwidth to 10MHz

0x1E

0x7C00

DRIVE_CURRENT_CH0 Sets sensor drive current on ch 0

0x1F

0x7C00

DRIVE_CURRENT_CH1 Sets sensor drive current on ch 1

0x20

0x7C00

DRIVE_CURRENT_CH2 Sets sensor drive current on ch 2

0x1A

0x1601

CONFIG

enable full current drive during sensor activation, select external clock

source, wake up device to start conversion. This register write must occur

last because device configuration is not permitted while the FDC is in active

mode.

10.2.3.3 Inductor Self-Resonant Frequency

Every inductor has a distributed parasitic capacitance, which is dependent on construction and geometry. At the

Self-Resonant Frequency (SRF), the reactance of the inductor cancels the reactance of the parasitic

capacitance. Above the SRF, the inductor will electrically appear to be a capacitor. Because the parasitic

capacitance is not well-controlled or stable, it is recommended that: fSENSOR < 0.8 × fSR.

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