FDC2114RGHT datasheet(14/60 Pages) TI1

14 / 60 page

FDC2212, FDC2214, FDC2112, FDC2114

SNOSCZ5A – JUNE 2015 – REVISED JUNE 2015

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Feature Description (continued)

Table 1. Clock Configuration Requirements

SET

VALID fREFx

VALID fINx

SET CHx_FIN_SEL

SET

MODE(1)

CLKIN SOURCE

CHx_SETTLECO

RANGE (MHz)

RANGE

to (2)

CHx_RCOUNT to

UNT to

Multi-channel

Internal

fREFx ≤ 55

Differential sensor

configuration:

External

fREFx ≤ 40

b01: 0.01MHz to

Single-channel

Either external or

fREFx ≤ 35

8.75MHz (divide by 1)

internal

b10: 5MHz to 10MHz

< fREFx /4

> 3

> 8

(divide by 2)

Single-ended sensor

configuration

b10: 0.01MHz to

10MHz (divide by 2)

(1)

Channels 2 and 3 are only available for FDC2114 and FDC2214.

(2)

Refer to Sensor Configuration for information on differential and single-ended sensor configurations.

Table 2 shows the clock configuration registers for all channels.

Table 2. Clock Configuration Registers

CHANNEL(1)

CLOCK

FIELD [ BIT(S) ]

VALUE

fCLK = Master

CONFIG, addr

REF_CLK_SRC [9]

b0 = internal oscillator is used as the

Clock Source

0x1A

master clock

All

b1 = external clock source is used as the

master clock

fREF0

CLOCK_DIVIDER

CH0_FREF_DIVIDER [9:0]

fREF0 = fCLK / CH0_FREF_DIVIDER

S_CH0, addr 0x14

fREF1

CLOCK_DIVIDER

CH1_FREF_DIVIDER [9:0]

fREF1 = fCLK / CH1_FREF_DIVIDER

S_CH1, addr 0x15

fREF2

CLOCK_DIVIDER

CH2_FREF_DIVIDER [9:0]

fREF2 = fCLK / CH2_FREF_DIVIDER

S_CH2, addr 0x16

fREF3

CLOCK_DIVIDER

CH3_FREF_DIVIDER [9:0]

fREF3 = fCLK / CH3_FREF_DIVIDER

S_CH3, addr 0x17

fIN0

CLOCK_DIVIDER

CH0_FIN_SEL [13:12]

fIN0 = fSENSOR0 / CH0_FIN_SEL

S_CH0, addr 0x14

fIN1

CLOCK_DIVIDER

CH1_FIN_SEL [13:12]

fIN1 = fSENSOR1 / CH1_FIN_SEL

S_CH1, addr 0x15

fIN2

CLOCK_DIVIDER

CH2_FIN_SEL [13:12]

fIN2 = fSENSOR2 / CH2_FIN_SEL

S_CH2, addr 0x16

fIN3

CLOCK_DIVIDER

CH3_FIN_SEL [13:12]

fIN3 = fSENSOR3 / CH3_FIN_SEL

S_CH3, addr 0x17

(1)

Channels 2 and 3 are only available for FDC2114 and FDC2214

9.3.2 Multi-Channel and Single-Channel Operation

The multi-channel package of the FDC enables the user to save board space and support flexible system design.

For example, temperature drift can often cause a shift in component values, resulting in a shift in resonant

frequency of the sensor. Using a second sensor as a reference provides the capability to cancel out a

temperature shift. When operated in multi-channel mode, the FDC sequentially samples the active channels. In

single-channel mode, the FDC samples a single channel, which is selectable. Table 3 shows the registers and

values that are used to configure either multi-channel or single-channel modes.

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