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C161PI Datasheet(PDF) 50 Page - Infineon Technologies AG |
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C161PI Datasheet(HTML) 50 Page - Infineon Technologies AG |
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50 / 82 page  &3, Data Sheet 48 1999-07 Direct Drive When pins P0.15-13 (P0H.7-5) equal 011 B during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of I CPU directly follows the frequency of IOSC so the high and low time of I CPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock I OSC. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCL min = 1/IOSC * DCmin (DC = duty cycle) For two consecutive TCLs the deviation caused by the duty cycle of I OSC is compensated so the duration of 2TCL is always 1/ I OSC. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula 2TCL = 1/ I OSC. Note: The address float timings in Multiplexed bus mode ( W 11 and W45) use the maximum duration of TCL (TCL max = 1/IOSC * DCmax) instead of TCLmin. |
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