 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
C161PI Datasheet(PDF) 68 Page - Infineon Technologies AG |
|
|
|||||||||||||||||||||||||||||
C161PI Datasheet(HTML) 68 Page - Infineon Technologies AG |
|
|
68 / 82 page  &3, Data Sheet 66 1999-07 Address hold after RdCS, WrCS W 55 CC -6 + W F –-6 + W F –ns Data hold after WrCS W 57 CC 6 + W F – TCL - 14 + W F –ns 1) RW-delay and W A refer to the next following bus cycle (including an access to an on-chip X-Peripheral). 2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. 3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below). Demultiplexed Bus (Standard Supply Voltage Range) (continued) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 W A + WC + WF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 25 MHz Variable CPU Clock 1 / 2TCL = 1 to 25 MHz Unit min. max. min. max. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
