Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

C161PI Datasheet(PDF) 51 Page - Infineon Technologies AG

Part # C161PI
Description  16-Bit Single-Chip Microcontroller
PDF  82 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

C161PI Datasheet(HTML) 51 Page - Infineon Technologies AG

Back Button C161PI Datasheet HTML 47Page - Infineon Technologies AG C161PI Datasheet HTML 48Page - Infineon Technologies AG C161PI Datasheet HTML 49Page - Infineon Technologies AG C161PI Datasheet HTML 50Page - Infineon Technologies AG C161PI Datasheet HTML 51Page - Infineon Technologies AG C161PI Datasheet HTML 52Page - Infineon Technologies AG C161PI Datasheet HTML 53Page - Infineon Technologies AG C161PI Datasheet HTML 54Page - Infineon Technologies AG C161PI Datasheet HTML 55Page - Infineon Technologies AG Next Button
Zoom Inzoom in Zoom Outzoom out
 51 / 82 page
background image
&3,
Data Sheet
49
1999-07
AC Characteristics
AC Characteristics
External Clock Drive XTAL1 (Standard Supply Voltage Range)
(Operating Conditions apply)
Parameter
Symbol
Direct Drive
1:1
Prescaler
2:1
PLL
1:N
Unit
min.
max.
min.
max.
min.
max.
Oscillator period
W
OSC SR
40
–
20
–
60
1)
1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation
mode. Please see respective table above.
500
1)
ns
High time
2)
2) The clock input signal must reach the defined levels
9
IL and 9IH2.
W
1
SR
20
3)
3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (
I
CPU) in
direct drive mode depends on the duty cycle of the clock input signal.
–6–10
–
ns
Low time
2)
W
2
SR
20
3)
–6–10
–
ns
Rise time
2)
W
3
SR
–10
–6–10
ns
Fall time 2)
W
4
SR
–10
–6–10
ns
External Clock Drive XTAL1 (Reduced Supply Voltage Range)
(Operating Conditions apply)
Parameter
Symbol
Direct Drive
1:1
Prescaler
2:1
PLL
1:N
Unit
min.
max.
min.
max.
min.
max.
Oscillator period
W
OSC SR
50
–
25
–
60
1)
1) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation
mode. Please see respective table above.
500
1)
ns
High time
2)
2) The clock input signal must reach the defined levels
9
IL and 9IH2.
W
1
SR
25
3)
3) The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (
I
CPU) in
direct drive mode depends on the duty cycle of the clock input signal.
–8–10
–
ns
Low time 2)
W
2
SR
25 3)
–8–10
–
ns
Rise time
2)
W
3
SR
–10
–6–10
ns
Fall time
2)
W
4
SR
–10
–6–10
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com