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C161PI Datasheet(PDF) 53 Page - Infineon Technologies AG |
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C161PI Datasheet(HTML) 53 Page - Infineon Technologies AG |
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53 / 82 page  &3, Data Sheet 51 1999-07 A/D Converter Characteristics (Operating Conditions apply) 4.0V (2.6V) ≤ 9 AREF ≤ 9DD + 0.1V (Note the influence on TUE.) 9 SS - 0.1V ≤ 9AGND ≤ 9SS + 0.2V Parameter Symbol Limit Values Unit Test Condition min. max. Analog input voltage range 9 AIN SR 9 AGND 9 AREF V 1) 1) 9 AIN may exceed 9AGND or 9AREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000 H or X3FFH, respectively. Basic clock frequency I BC 0.5 6.25 MHz 2) 2) The limit values for I BC must not be exceeded when selecting the CPU frequency and the ADCTC setting. Conversion time W C CC –40 W BC + W S+2WCPU 3) W CPU = 1 / ICPU 3) This parameter includes the sample time W S, the time for determining the digital result and the time to load the result register with the conversion result. Values for the basic clock W BC depend on the conversion time programming. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. Total unadjusted error TUE CC 4) 4) TUE is tested at 9 AREF=5.0V (3.3V), 9AGND=0V, 9DD=4.9V (3.2V). It is guaranteed by design for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see , OV specification) occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be ±4 LSB (±8 LSB @ 3V). – ± 2 LSB 9 AREF ≥ 4.0 V 5) 5) This case is not applicable for the reduced supply voltage range. – ± 4 LSB 9 AREF ≥ 2.6 V Internal resistance of reference voltage source 5 AREF SR – W BC / 60 - 0.25 k Ω W BC in [ns] 6) 7) 6) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within each conversion step. The maximum internal resistance results from the programmed conversion timing. 7) Not 100% tested, guaranteed by design. Internal resistance of analog source 5 ASRC SR – W S / 450 - 0.25 k Ω W S in [ns] 7) 8) 8) During the sample time the input capacitance & I can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within W S. After the end of the sample time W S, changes of the analog input voltage have no effect on the conversion result. Values for the sample time W S depend on programming and can be taken from the table below. ADC input capacitance & AIN CC – 33 pF 7) |
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