GS1670 datasheet(119/126 Pages) SEMTECH

119 / 126 page

GS1670 HD/SD SDI Receiver

Data Sheet

53831 - 2

September 2012

119 of 126

4.21 JTAG Test Operation

When the JTAG/HOST pin of the GS1670 is set HIGH, the host interface port is

configured for JTAG test operation. In this mode, pins E7, F8, F7, and E8 become TDO,

TCK, TMS, and TDI. In addition, the RESET_TRST pin operates as the test reset pin.

Boundary scan testing using the JTAG interface is enabled in this mode.

There are two ways in which JTAG can be used:

1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test

Equipment) during PCB assembly.

2. Under control of a host processor for applications such as system power on self

tests.

When the JTAG tests are applied by ATE, care must be taken to disable any other devices

driving the digital I/O pins. If the tests are to be applied only at ATE, this can be

accomplished with tri-state buffers used in conjunction with the JTAG/HOST input

signal. This is shown in Figure 4-43.

Figure 4-43: In-Circuit JTAG

Alternatively, if the test capabilities are to be used in the system, the host processor may

still control the JTAG/HOST input signal, but some means for tri-stating the host must

exist in order to use the interface at ATE. This is represented in Figure 4-44.

Figure 4-44: System JTAG

Scan coverage is limited to digital pins only. There is no scan coverage for analog pins

VCO, SDO/SDO, RSET, LF, and CP_RES.

The JTAG/HOST pin must be held LOW during scan and therefore has no scan coverage.

Please contact your Semtech representative to obtain the BSDL model for the GS1670.

Application HOST

CS_TMS

SCLK_TCK

SDIN_TDI

SDOUT_TDO

JTAG_HOST

In-circuit ATE probe

GS1670

Application HOST

CS_TMS

SCLK_TCK

SDIN_TDI

SDOUT_TDO

JTAG_HOST

In-circuit ATE probe

Tri-State

GS1670

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