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GS1670 Datasheet(PDF) 121 Page - Semtech Corporation |
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GS1670 Datasheet(HTML) 121 Page - Semtech Corporation |
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121 / 126 page  GS1670 HD/SD SDI Receiver Data Sheet 53831 - 2 September 2012 121 of 126 5. Application Reference Design 5.1 Typical Application Circuit CD_VDD CS10-27.000M 16p 16p CD_VDD AUDIO WORD CLOCK 10n +1.2V_A 0R 0R 10n +1.2V 10n 10n 10n 10n 4. For impedance controlled signal layout refer to PCB layout guide. IO_VDD +1.2V DOUT[19:0] 10n Power Filtering 10n 10n AUDIO OUTPUT CH 1 & 2 SDIN_TDI DNP SCLK_TCK 4u7 22R 22R 10n 49R9 49R9 Close to pin 1 & 2 of GS2978 AUDIO OUTPUT CH 3 & 4 CS_TMS +1.2V_A IO_VDD +3.3V_A R7 105R +1.2V C18 33u +1.2V_A LOCKED (DEFAULT, PROGRAMMABLE) 22R R19 DNP +3.3V_A 22R 0R 10n 10n Place close to GS1670 AUDIO OUTPUT CH 5 & 6 1 UCBBJE20-1 CD_DISABLEb Y/1ANC (DEFAULT, PROGRAMMABLE) PCLK 22R DATA_ERRORb (DEFAULT, PROGRAMMABLE) 1u 22R AUDIO OUTPUT CH 7 & 8 H/HSYNC (DEFAULT, PROGRAMMABLE) 1u A_GND 22R 10n CD SLEW RATE SELECT VBG A1 LF A2 LB_CONT A3 STAT0 A5 STAT1 A6 STAT2 B5 STAT3 B6 STAT4 C5 STAT5 C6 PCLK A8 DOUT 0 K8 DOUT 1 J8 DOUT 2 K9 DOUT 3 K10 DOUT 4 J9 DOUT 5 J10 DOUT 6 H9 DOUT 7 H10 DOUT 8 F9 DOUT 9 F10 DOUT 10 E9 DOUT 11 E10 DOUT 12 C8 DOUT 13 C10 DOUT 14 C9 DOUT 15 B10 DOUT 16 B9 DOUT 17 A10 DOUT 18 A9 DOUT 19 B8 RSV B3 SDI C1 RESET_TRST C7 SDI D1 SW_EN D7 JTAG/HOST D8 SDOUT_TDO E7 SDIN_TDI E8 TERM F1 RSV F2 CS_TMS F7 SCLK_TCK F8 RSV G1 RSV G2 RC_BYP G3 RSV G4 SMPTE_BYPASS G7 DVB_ASI G8 AUDIO_EN/DIS H3 WCLK H4 TIM_861 H5 XTAL_OUT H6 20BIT/10BIT H7 IOPROC_EN/DIS H8 SDO J1 SDO_EN/DIS J2 AOUT_1/2 J3 ACLK J4 AOUT_5/6 J5 XTAL2 J6 SDO K1 STANDBY K2 AOUT_3/4 K3 AMCLK K4 AOUT_7/8 K5 XTAL1 K6 GS1670-IBE3 SMPTE_BYPASS 1u Place close to GS1670 +3.3V_A 10n V/VSYNC (DEFAULT, PROGRAMMABLE) 22R 1u F/DE (DEFAULT, PROGRAMMABLE) 22R 22R 22R 3. For analog power and ground isolation refer to PCB layout guide. DVB_ASI 1u Power Decoupling 22R 1u Place close to GS1670 22R SDOUT_TDO SW_EN 1u 22R AUDIO_EN/DIS 1u EQ_VCC 22R IOPROC_EN/DIS 75-ohm Traces CD_DISABLEb 22R 75R 4u7 20BIT/10BIT 75R 5n6 10n +3.3V_A 10n 10n 1 UCBBJE20-1 22R RC_BYP 75R 75R IO_VDD 1u 22R JTAG/HOST EQ_VCC EQ_VCC SDIN 2 SDIN 3 VEE 4 SDO 10 SDO 11 VEE 1 VEE 9 VEE 12 GS2984/ GS2974 470n 75R 6n2 75R 22R 1u 37R4 1u 10n 10n 470n 22R STANDBY RESET_TRST 22R 2. The value of the series resistors on video data, clock, and timing connections should be determined by board signal integrity test. 22R 22R 22R SDO_EN/DIS 0R 22R 10n 10n +3.3V TP CD_VDD 0R 10n 10n 47n SDI 2 VEE 3 RSET 4 SD/HD 10 SDO 11 SDI 1 VCC 9 SDO 12 GS2978-CNE3 10n +1.2V_A 10n 10n 22R 10n AUDIO MASTER CLOCK 10n DOUT[19:0] TIM_861 22R 750R 1. DNP (Do Not Populate). Notes: AUDIO SERIAL BIT CLOCK 1u Close to pin C1 & D1 of GS1670 A_GND A_GND A_GND A_GND A_GND A_GND A_GND A_GND A_GND A_GND A_GND A_GND A_GND A_GND A_GND A_GND CD_VDD A_GND A_GND A_GND A_GND A_GND A_GND A_GND 10n |
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