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GS2971 Datasheet(PDF) 97 Page - Semtech Corporation

Part # GS2971
Description  3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Audio and Video Processing
PDF  148 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS2971 Datasheet(HTML) 97 Page - Semtech Corporation

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GS2971 3Gb/s, HD, SD SDI Receiver
Data Sheet
45898 - 2
September 2012
97 of 148
000h
IOPROC_1
ANC_CHECKSUM
_INSERTION_DS1_MASK
3Disables insertion of ancillary data
checksums for 3G Level B Data
Stream 1, 3G Level A, HD and SD
inputs.
R/W
0
CRC_INS_DS1_MASK2
Disables insertion of HD/3G CRC
words for 3G Level B Data Stream
1, 3G Level A, and HD inputs.
R/W
0
LNUM_INS_DS1_MASK1
Disables insertion of line numbers
for 3G Level B Data Stream 1, 3G
Level A, and HD inputs.
R/W
0
TRS_INS_DS1_MASK0
Disables insertion of TRS words for
3G Level B Data Stream 1, 3G Level
A, HD and SD inputs.
R/W
0
001h
IOPROC_2
RSVD
15-13
Reserved.
R/W
N/A
TRS_WORD_REMAP_DS2
_DISABLE
12
Disables 8-bit TRS word remapping
in Data Stream 2 (3G Level B only).
R/W
0
RSVD
11
Reserved.
R/W
0
REGEN_352M_MASK10
Disables regeneration of the
SMPTE 352M packet for 3G Level B
data. Note: this bit needs to be
enabled via the host interface to
disable SMPTE 352M packet
generation. It is strongly
recommended to set this bit LOW
only when Level B to Level A
conversion is enabled.
R/W
0
DS_SWAP_3G
9
Swaps Data Stream 1 (DS1) and
Data Stream 2 (DS2) at the output
in 3G mode.
In 20-bit output mode, DS1 shall be
present on DOUT pins [19:10] and
DS2 shall be present on DOUT pins
[9:0] by default. When
DS_SWAP_3G is set to '1', DS2 shall
be present on DOUT pins [19:10]
and DS1 shall be present on DOUT
pins [9:0]
In 10-bit (DDR) output mode, DS2
shall precede DS1 by default. When
DS_SWAP_3G is set to '1', DS1 shall
precede DS2.
R/W
0
LEVEL_B2A_CONV
_DISABLE_MASK
8Disable conversion of a 3G Level B
input to a 3G Level A format. Only
effective if in 3G Level B mode.
Default is active HIGH (disabled), so
Level B inputs are formatted as
Level B outputs.
R/W
1
Table 4-29: Video Core Configuration and Status Registers (Continued)
Address
Register Name
Bit Name
Bit
Description
R/W
Default



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