GS2971 datasheet(32/148 Pages) SEMTECH

32 / 148 page

GS2971 3Gb/s, HD, SD SDI Receiver

Data Sheet

45898 - 2

September 2012

32 of 148

The edge energy of the equalized signal is monitored by a detector circuit which

produces an error signal corresponding to the difference between the desired edge

energy and the actual edge energy. This error signal is integrated by both an internal and

an external AGC filter capacitor providing a steady control voltage for the gain stage. As

the frequency response of the gain stage is automatically varied by the application of

negative feedback, the edge energy of the equalized signal is kept at a constant level

which is representative of the original edge energy at the transmitter. The equalized

signal is also DC restored, effectively restoring the logic threshold of the equalized signal

to its correct level independent of shifts due to AC coupling.

Figure 4-3: GS2971 Integrated EQ Block Diagram

4.4 Serial Digital Loop-Through Output

The GS2971 contains a 100

Ω differential serial output buffer which can be configured to

output either a retimed or a buffered version of the serial digital input. The SDO and SDO

outputs of this buffer can interface directly to a 3Gb/s-capable, SMPTE compliant

Gennum cable driver. See 5.3 Typical Application Circuit on page 143.

When the RC_BYP pin is set HIGH, the serial digital output is the re-timed version of the

serial input.

When the RC_BYP pin is set LOW, the serial digital output is simply the buffered version

of the serial input, bypassing the internal reclocker.

The output can be disabled by setting the SDO_EN/DIS pin LOW. The output is also

disabled when the STANDBY pin is asserted HIGH. When the output is disabled, both

SDO and SDO pins are set to VDD and remain static.

The SDO output is muted when the RC_BYP pin is set HIGH and the PLL is unlocked

(LOCKED pin is LOW). When muted, the output is held static at logic ‘0’ or logic ‘1’.

NOTE: the serial digital output is muted when the GS2971 is unlocked.

Equalizer

Output

AGC

SDI

SDO

SDI

SDO

AGC

GAIN_SEL

Restore

Table 4-1: Serial Digital Output

SDO_EN/DIS

RC_BYP

SDO/SDO

Disabled

Re-timed

Buffered (not re-timed)

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