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DS92UT16 Datasheet(PDF) 21 Page - Texas Instruments

Part # DS92UT16
Description  UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers
PDF  111 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DS92UT16 Datasheet(HTML) 21 Page - Texas Instruments

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OBSOLETE
DS92UT16
www.ti.com
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
ATM Polling
When configured as an ATM Layer device, the DS92UT16 polls the connected PHY ports using the MPhy
address busses U_TxAddr and U_RxAddr. Only those ports which are connected will be polled. The connected
ports list defined in the UCPL3–UCPL0 registers is used to determine which ports are connected. The PHY ports
respond on U_TxCLAV[7:0] and U_RxCLAV[7:0]. The MPhy address determines the Port and the CLAV pin
number determines the sub-port. Therefore up to 8 sub-ports may be connected to a port. Polling of a single
MPhy address will get eight responses on the eight CLAV lines. The DS92UT16 uses the connected sub-port list
defined in the UCSPL register to determine which of these eight sub-port responses are valid. On reset, the
UCPL3–UCPL0 registers are all set to 0xFF and the UCSPL register is set to 0x01, so the DS92UT16 will poll all
ports and assume only sub-port zero is connected.
PHY Polling
When configured as a PHY Layer device, the DS92UT16 is polled by the connected ATM device. During polling,
the DS92UT16 will only respond to MPhy addresses on U_TxAddr and U_RxAddr, which are defined as
connected. The connected ports list defined in the UCPL3–UCPL0 registers is used to determine which ports are
connected. On reset the UCPL3–UCPL0 registers are all set to 0xFF so the DS92UT16 will respond to all MPhy
addresses during polling.
NOTE
There must always be at least one connected port defined in the UCPL3–UCPL0
registers. If no ports are to be connected then use Configuration Traffic Inhibit mode
described in Configuration and Traffic Inhibit Operation.
Sub-Port Address
The operation of the sub-port address is illustrated in Figure 10. To use the Extended Level 2 mode that allows
addressing up to 248 Ports, the ATM Layer (that which drives the DS92UT16 in PHY mode) must be capable of
inserting a three bit sub-port address in the PDU cell for use by the DS92UT16. This 3-bit sub-port address must
reside in either the User Prepend, Cell Header, or UDF bytes. It’s location is defined in the UTOPIA Sub-Port
Address Location (USPAL) and UTOPIA Sub-Port Address Mask (USPAM) registers. The USPAL register
defines which byte of the User Prepend, Cell Header, or UDF, contains the address and the USPAM register
defines which three bits of that byte are the sub-port address.
Transmit Path Example: The MPhy address is interpreted as the Port address. So, a cell destined for the PHY
designated as Port 0 Sub-Port 7 has the three bit sub-port address 7 (binary “111”) inserted into the defined sub-
port address location of the PDU cell by the ATM layer head-end. It is then transmitted to the DS92UT16 in PHY
mode using MPhy address 0. The DS92UT16 in PHY mode does not examine the sub-port address because all
cells are transmitted down-bridge anyway.
At the far end, the DS92UT16 in ATM mode extracts the sub-port address. This is used to determine which sub-
port CLAV/ENB signals the destination PHY is connected to. A port address of 0 and a sub-port address of 7
means that the destination PHY is MPhy address 0 attached to U_TxENB[7] and U_TxCLAV[7]. The cell is then
transmitted to that PHY.
Copyright © 2002–2013, Texas Instruments Incorporated
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