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DS92UT16 Datasheet(PDF) 49 Page - Texas Instruments |
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DS92UT16 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 111 page  OBSOLETE DS92UT16 www.ti.com SNOS992E – JANUARY 2002 – REVISED APRIL 2013 Register Description This section describes all the software accessible registers in the DS92UT16. A summary of all registers is shown in Table 19. Table 19. Register Map Summary(1)(2)(3) Software Reset Register Name Address Section and Description Lock Value SLK0 0x00 N 0x00 18.1 Software Lock 1 SLK1 0x01 N 0x00 18.1 Software Lock 2 VID 0x02 N See(4) 18.2 Version Identification GCS 0x03 Y 0x05 18.3 General Control and Status LVC 0x04 Y 0x3B 18.4 LVDS Control PDUCFG 0x05 Y 0x00 18.5 PDU Configuration IS 0x06 N 0x00 18.6 Interrupt Source ISE 0x07 N 0x00 18.7 Interrupt Source Enables LKSC 0x08 Y 0x34 18.8 Link Status and Control TXLL 0x09 N 0x00 18.9 Transmit Link Label ETXRXA 0x0A N 0x01 18.10 ECC Transmit Buffer and Receive LVDS Alarms ETXRXIE 0x0B N 0x00 18.11 ECC Transmit Buffer and Receive LVDS Interrupt Enables ETXSD 0x0C N 0x00 18.12 ECC Transmit Buffer Send ETXD7 0x0D N 0x00 18.13 ECC Transmit Buffer 7 ETXD6 0x0E N 0x00 18.13 ECC Transmit Buffer 6 ETXD5 0x0F N 0x00 18.13 ECC Transmit Buffer 5 ETXD4 0x10 N 0x00 18.13 ECC Transmit Buffer 4 ETXD3 0x11 N 0x00 18.13 ECC Transmit Buffer 3 ETXD2 0x12 N 0x00 18.13 ECC Transmit Buffer 2 ETXD1 0x13 N 0x00 18.13 ECC Transmit Buffer 1 ETXD0 0x14 N 0x00 18.13 ECC Transmit Buffer 0 GPIO 0x15 N 0xF0 18.14 General Purpose Input/Output TERRCTL 0x16 Y 0x00 18.15 Test Error Control ERRBIP1 0x17 Y 0x00 18.16 BIP Error Mask 1 ERRBIP0 0x18 Y 0x00 18.16 BIP Error Mask 0 ERRHEC 0x19 Y 0x00 18.17 HEC Error Mask 0 ALBC 0x1A N 0x00 18.18 ATM and LVDS Loopback Control ALBMP 0x1B N 0x00 18.19 ATM Loopback Cell MPhy ALBCF3 0x1C N 0x00 18.20 ATM Loopback Cell Format 3 ALBCF2 0x1D N 0x00 18.20 ATM Loopback Cell Format 2 ALBCF1 0x1E N 0x00 18.20 ATM Loopback Cell Format 1 ALBCF0 0x1F N 0x00 18.20 ATM Loopback Cell Format 0 RALL 0x20 N 0x00 18.21 Receive Port A Link Label RAELL 0x21 N 0x00 18.22 Receive Port A Expected Link Label RALA 0x22 N 0x00 18.23 Receive Port A Local Alarms RALIE 0x23 N 0x00 18.24 Receive Port A Local Interrupt Enables RACTL 0x24 Y 0x01 18.25 Receive Port A Control Reserved 0x25 ERAD7 0x26 N 0x00 18.26 ECC Receive Buffer A 7 (1) All configuration and control registers can be read by the processor to determine the status of the DS92UT16. (2) All reserved (register bits for internal use only) and unused (no register) bits will be read as zero and should be written as zero to ensure future compatibility. (3) Writing to read only register bits has no affect. (4) The reset value of the VID register will be different for various versions of the device. Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Links: DS92UT16 |
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