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DS92UT16 Datasheet(PDF) 16 Page - Texas Instruments

Part # DS92UT16
Description  UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers
PDF  111 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DS92UT16 Datasheet(HTML) 16 Page - Texas Instruments

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OBSOLETE
DS92UT16
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
www.ti.com
Signal Description
Package ball assignment in Package
PIN DESCRIPTION
Internal
Signal Name
Description
Width
Signal Type
Polarity
Bias
UTOPIA INTERFACE
U_TxData [15:0]
Transmit toward the PHY Layer data bus.
16
BiDir(1)
U_TxParity
Transmit data bus parity bit. (odd parity)
1
BiDir(1)
U_TxCLAV [7:1]
Transmit cell available - Extended.
7
Input(2)
Active High
Pull Down
U_TxCLAV [0]
Transmit cell available - Normal/Extended.
1
BiDir(3)
Active High
Pull Down
U_TxENB [7:1]
Enable Data transfers - Extended.
7
Output(2)
Active Low
U_TxENB [0]
Enable Data transfers - Normal/Extended.
1
BiDir(1)
Active Low
U_TxSOC
Transmit Start Of Cell.
1
BiDir(1)
Active High
U_TxAddr [4:0]
Address of MPHY device being selected.
5
BiDir(1)
U_RxData [15:0]
Receive from the PHY Layer data bus.
16
BiDir(3)
U_RxParity
Receive data bus parity bit. (odd parity)
1
BiDir(3)
U_RxCLAV [7:1]
Receive cell available - Extended.
7
Input(2)
Active High
Pull Down
U_RxCLAV [0]
Receive cell available - Normal/Extended.
1
BiDir(3)
Active High
Pull Down
U_RxENB [7:1]
Enable Data transfers - Extended.
7
Output(2)
Active Low
U_RxENB [0]
Enable Data transfers - Normal/Extended.
1
BiDir(1)
Active Low
U_RxSOC
Receive Start Of Cell.
1
BiDir(3)
Active High
U_RxAddr [4:0]
Address of MPHY device being selected.
5
BiDir(1)
U_UDBClk
UTOPIA Down Bridge - Input transfer clock.
1
Input(4)
U_UUBClk
UTOPIA Up Bridge - Output transfer clock.
1
Input(5)
LVDS INTERFACE
LVDS_ADout[+,
−]
A Serial data differential outputs.
2
Output
LVDS_BDout[+,
−]
B Serial data differential outputs.
2
Output
LVDS_ADenb
Serial transmit data A output enable.
1
Input
Active High
Pull Up
LVDS_BDenb
Serial transmit data B output enable.
1
Input
Active High
Pull Up
LVDS_Synch
External control to transmit SYNCH patterns on serial
1
Input
Active High
Pull Down
interface.
LVDS_TxClk
Transmit clock.
1
Input
LVDS_TxPwdn
Transmit section power down
1
Input
Active Low
Pull Up
LVDS_ADin[+,
−]
PortA Serial data differential inputs.
2
Input
LVDS_ALock_n
PortA Clock recovery lock status
1
Output
LVDS_ARxClk
PortA Recovered clock.
1
Output
LVDS_ARefClk
PortA Reference clock for receive PLLs.
1
Input
LVDS_APwdn
PortA Power Down.
1
Input
Active Low
Pull Up
LVDS_BDin[+,
−]
PortB Serial data differential inputs.
2
Input
LVDS_Block_n
PortB Clock recovery lock status.
1
Output
LVDS_BRxClk
PortB Recovered clock.
1
Output
LVDS_BRefClk
PortB Reference clock for receive PLLs.
1
Input
LVDS_BPwdn
PortB Power Down.
1
Input
Active Low
Pull Up
(1)
These pins are Outputs in ATM Layer mode and Inputs PHY Layer mode.
(2)
These pins are only used in PHY layer mode, Extended 248 PHY mode. In Normal 31 PHY mode or ATM layer mode, they must be
unconnected.
(3)
These pins are Inputs in ATM Layer mode and Outputs PHY Layer mode
(4)
In PHY layer mode this is the Utopia TxClk and in ATM layer mode this is the Utopia RxClk.
(5)
In PHY layer mode this is the Utopia RxClk and in ATM layer mode this is the Utopia TxClk.
16
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