DS92UT16 datasheet(7/111 Pages) TI1

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DS92UT16

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SNOS992E – JANUARY 2002 – REVISED APRIL 2013

Parity generation and checking is available in all modes.

To support systems where routing tags and/or padding are added to the ATM cells at a previous device, the

UTOPIA interface on DS92UT16 may be programmed to handle non-standard ATM cells of length 52 bytes up to

64 bytes. See Figure 6. In all cases, the Start Of Cell (SOC) signal must correspond to the first byte or word of

the extended cell.

Back-to-back cell transfer is supported in all modes.

When configured as an ATM layer device, receive polling and transmit polling of those Ports with queued cells is

Round-Robin. The DS92UT16 will only poll those PHY ports configured as active.

TRAFFIC BUFFERS

Down-Bridge FIFO

In the down-bridge direction, a simple 3 cell FIFO (with 30 cell overhead) is used to rate adapt the data from the

UTOPIA clock domain to the LVDS clock domain for transmission. Per port queuing and back pressure/flow

control is handled by the corresponding up-bridge Multi-port Traffic Buffer in the far end DS92UT16 device as

described in Up-Bridge Multi-Port Traffic Buffer and Flow Control.

Up-Bridge Multi-Port Traffic Buffer

In the up-bridge direction, a 160 cell linked list buffer is shared across up to 31 port queues. This is called the

Multi-port Traffic Buffer. Although each MPHY may be connected to 8 sub-ports/PHY's, the MTB has a single

queue per MPHY port, as it only uses the 5-bit MPHY address and does not access the sub-port address bits.

Each port has a programmable upper fill threshold. In the up-bridge direction, queue overflow is avoided through

the means of a per queue flow control protocol embedded in the LVDS link as described in Flow Control. Should

any queue reach this upper threshold, back-pressure is applied via the flow control mechanism over the serial

link to the down-bridge (transmitting) device which uses the normal UTOPIA flow control handshaking to prevent

any more cells being transferred and thus prevent overflow.

The individual queue per port architecture ensures that the flow control is non-blocking across the 31 ports.

However, the 8 sub-ports within each port can be blocking.

Furthermore, as is the nature of link-list buffers, each queue may be over-assigned memory space, working on

the assumption that not every queue will back up simultaneously. To accommodate the rare occasions where the

buffer as a whole approaches full but individual queues are below their full threshold, the device also compares

the overall buffer fill against a threshold. The flow control mechanism provides a global ‘halt' command to ensure

that no cells will be lost if the overall buffer should approach the overflow condition.

TRANSMISSION CONVERGENCE SUB-LAYER (TCS)

In the down-bridge direction, the Transmission Convergence Sub-layer (TCS) Assembler performs cell rate de-

coupling. The TCS Assembler then prepares the cells for transport over the LVDS link by packaging them within

link Transport Containers (TC).

In the up-bridge direction, the TCS Disassemblers unpack the link transport containers and route the cells to the

Multi-port Traffic Buffer.

MPHY address, flow control, and OAM information is embedded within the link transport containers.

Cell Rate Decoupling

In the down-bridge direction, the TCS Assembler inserts idle cells when no valid traffic cells are available from

the FIFO for onward transmission. In the up-bridge direction, the TCS Disassembler rejects all received idle cells.

Link Transport Container (TC)

The ATM cells received on the UTOPIA interface can be standard or user-specified cells. Cell length is

programmable from 52 to 64 bytes. These cells are treated as Protocol Data Units (PDU), which are packaged

into Transport Containers (TC) for transmission over the serial link. In the reverse direction, the cell PDUs are

unpacked from the link TCs before being passed out on the UTOPIA interface.

This is illustrated in Figure 6.

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