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DS92UT16 Datasheet(PDF) 79 Page - Texas Instruments

Part # DS92UT16
Description  UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers
PDF  111 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DS92UT16 Datasheet(HTML) 79 Page - Texas Instruments

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OBSOLETE
DS92UT16
www.ti.com
SNOS992E – JANUARY 2002 – REVISED APRIL 2013
RECEIVE PORT B REMOTE STATUS AND ALARMS—0x7C RBRA
Table 71. RBRA
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
RBRCS
RBRLOSA
RBRLOSB
RBRBA
RBRDSLL
Type: Bits[4:2] and [0] Read only/Clear on Read
Bit[1] Read only
Software Lock: No
Reset Value: 0x0D
The Receive Port B Remote Status and Alarms register contains information on the status of the far-end device,
which is connected to Port B. On a local Loss of Signal on Port B, LLOSB alarm, these bits return to their reset
values. When set, the RBRLOSA, RBRLOSB, RBRBA, and RBRDSLL bits will raise an interrupt if the
corresponding interrupt enable is set. Also, a change in value on RBRLOSA, RBRLOSB, RBRDSLL or RBRBA
will set the RBRCS bit. When set, the RBRCS bit will raise an interrupt if the corresponding interrupt enable is
set.
•
RBRCS Receive Port B, Remote Change of Status at far end device LVDS receive Ports.
•
RBRLOSA Receive Port B, Remote Loss Of Signal at far end device LVDS receive Port A.
•
RBRLOSB Receive Port B, Remote Loss Of Signal at far end device LVDS receive Port B.
•
RBRBA Receive Port B, Remote far end device active receive Port. Set = Port B active and Clear = Port A
active. Note that this bit, if set, will not clear on a read of this register.
•
RBRDSLL Receive Port B, Remote far end device active receive port Descrambler Loss of Lock. Set = Out of
Lock and Clear = Lock.
RECEIVE PORT B REMOTE INTERRUPT ENABLES—0x7D RBRIE
Table 72. RBRIE
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
RBRCSIE
RBRLOSAI
RBRLOSBI
RBRBAIE
RBRDSLLIE
E
E
Type: Read/Write
Software Lock: No
Reset Value: 0x00
This register contains the interrupt enables for the alarms in the RBRB register. Set = interrupt enabled and Clear
= interrupt disabled.
Copyright © 2002–2013, Texas Instruments Incorporated
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