ATMEGA323 datasheet(88/247 Pages) ATMEL

88 / 247 page

ATmega323(L)

1457G–AVR–09/03

Asynchronous Data

Reception

The USART includes a clock recovery and a data recovery unit for handling asynchro-

nous data reception. The clock recovery logic is used for synchronizing the internally

generated baud rate clock to the incoming asynchronous serial frames at the RxD pin.

The data recovery logic samples and low pass filters each incoming bit, thereby improv-

ing the noise immunity of the Receiver. The asynchronous reception operational range

depends on the accuracy of the internal baud rate clock, the rate of the incoming

frames, and the frame size in number of bits.

Asynchronous Clock

Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig-

ure 49 illustrates the sampling process of the start bit of an incoming frame. The sample

rate is 16 times the baud rate for normal mode, and 8 times the baud rate for Double

Speed mode. The horizontal arrows illustrate the synchronization variation due to the

sampling process. Note the larger time variation when using the double speed mode

(U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is

idle (i.e. no communication activity).

Figure 49. Start Bit Sampling

When the clock recovery logic detects a high (idle) to low (start) transition on the RxD

line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sam-

ple as shown in the figure. The clock recovery logic then uses samples 8, 9 and 10 for

Normal mode, and samples 4, 5 and 6 for Double Speed mode (indicated with sample

numbers inside boxes on the figure), to decide if a valid start bit is received. If two or

more of these three samples have logical high levels (the majority wins), the start bit is

rejected as a noise spike and the Receiver starts looking for the next high to low-transi-

tion. If however, a valid start bit is detected, the clock recovery logic is synchronized and

the data recovery can begin. The synchronization process is repeated for each start bit.

Asynchronous Data Recovery

When the Receiver clock is synchronized to the start bit, the data recovery can begin.

The data recovery unit uses a state machine that has 16 states for each bit in Normal

mode and 8 states for each bit in Double Speed mode. Figure 50 shows the sampling of

the data bits and the parity bit. Each of the samples is given a number that is equal to

the state of the recovery unit.

Figure 50. Sampling of Data and Parity Bit

START

IDLE

BIT 0

123

678

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

BIT n

123

678

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

ATMEGA323 Datasheet(PDF) 88 Page - ATMEL Corporation

ATMEGA323 Datasheet(HTML) 88 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL