ATMEGA323 datasheet(39/247 Pages) ATMEL

39 / 247 page

ATmega323(L)

1457G–AVR–09/03

Sleep Modes

To enter any of the six sleep modes, the SE bit in MCUCR must be set (one) and a

SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the MCUCR Reg-

ister select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save,

Standby or Extended Standby) will be activated by the SLEEP instruction. See Table 8

for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the

MCU wakes up. The MCU is then halted for four cycles, executes the interrupt routine,

and resumes execution from the instruction following SLEEP. The contents of the Reg-

ister File, SRAM, and I/O Memory are unaltered when the device wakes up from sleep.

If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset

Vector.

Idle Mode

When the SM2..0 bits are set to 000, the SLEEP instruction makes the MCU enter Idle

mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire

Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue oper-

ating. This enables the MCU to wake up from external triggered interrupts as well as

internal ones like the Timer Overflow and USART Transmit Complete interrupts. If

wake-up from the Analog Comparator interrupt is not required, the Analog Comparator

can be powered down by setting the ACD-bit in the Analog Comparator Control and Sta-

tus Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is

enabled, a conversion starts automatically when this mode is entered.

ADC Noise Reduction Mode

When the SM2..0 bits are set to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the MCU but allowing the ADC, the external interrupts,

the Two-wire Serial Interface address watch, Timer/Counter2 and the Watchdog to con-

tinue operating (if enabled). This improves the noise environment for the ADC, enabling

higher resolution measurements. If the ADC is enabled, a conversion starts automati-

cally when this mode is entered. Apart form the ADC Conversion Complete interrupt,

only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Inter-

face address match interrupt, or an external level interrupt on INT0 or INT1, or an

external edge interrupt on INT2, can wake up the MCU from ADC Noise Reduction

mode. A Timer/Counter2 Output Compare or overflow event will wake up the MCU, but

will not generate an interrupt unless Timer/Counter2 is clocked asynchronously.

In future devices this is subject to change. It is recommended for future code compatibil-

ity to disable Timer/Counter2 interrupts during ADC Noise Reduction mode if the

Timer/Counter2 is clocked synchronously.

Table 10. Interrupt 0 Sense Control

ISC01

ISC00

Description

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

ATMEGA323 Datasheet(PDF) 39 Page - ATMEL Corporation

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