ATMEGA323 datasheet(30/247 Pages) ATMEL

30 / 247 page

ATmega323(L)

1457G–AVR–09/03

Figure 28. Brown-out Reset During Operation

The hysteresis on V

BOT: VBOT+ = VBOT + 25 mV, VBOT- = VBOT - 25 mV

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle dura-

tion. On the falling edge of this pulse, the delay timer starts counting the Time-out Period

TOUT. Refer to page 64 for details on operation of the Watchdog Timer.

Figure 29. Watchdog Reset During Operation

MCU Control and Status

The MCU Control and Status Register contains control bits for general MCU functions,

and provides information on which reset source caused an MCU Reset.

• Bit 7 – JTD: JTAG Interface Disable

When this bit is cleared (zero), the JTAG interface is enabled if the JTAGEN Fuse is

programmed. If this bit is set (one), the JTAG interface is disabled. To avoid uninten-

tional disabling of the JTAG interface, the user software must write this bit as one twice

within four cycles to set the bit.

If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be

set to one. The reason for this is to avoid static current at the TDO pin in the JTAG

interface.

VCC

RESET

TIME-OUT

INTERNAL

RESET

VBOT-

VBOT+

tTOUT

Bit

654321

$34 ($54)

JTD

ISC2

–

JTRF

WDRF

BORF

EXTRF

PORF

MCUCSR

Read/Write

R/W

Initial Value

See Bit Description

ATMEGA323 Datasheet(PDF) 30 Page - ATMEL Corporation

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