OBSOLETE

CLC412

SNOS833D – AUGUST 2000 – REVISED APRIL 2013

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Figure 38.

The measurements were performed with SMT components using the recommended value of feedback resistor of

634

Ω at a gain of +2V/V. The pulse response plot labeled “Pulse Matching” found below shows the group delay

matching between amplifiers of the CLC412. The circuit topology is described in Figure 38.

Figure 39. Large Signal Pulse Response

The CLC412's amplifiers, built on the same die, provide the advantage of having tightly matched DC

characteristics. The typical DC matching specifications of the CLC412 are:

ΔVio = ±0.60mV, Δlbn = ±0.25µA, Δlbi = ±1.5µA.

Slew Rate and Settling Time

One of the advantages of current-feedback topology is an inherently high slew rate which produces a wider full

power bandwidth. The CLC412 has a typical slew rate of 1300V/µs. The required slew rate for a design can be

calculated by the following equation:

SR = 2

(2)

14

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