18

S2060

GIGABIT ETHERNET TRANSCEIVER

March 7, 2001 / Revision H

OTHER OPERATING MODES

Loopback Mode

The S2060 supports internal loopback mode in

which the serial data from the transmitter replaces

external serial data. The loopback function is en-

abled when the loopback enable signal, EWRAP, is

set ACTIVE.

The loopback mode provides the ability to perform

system diagnostics and to perform off-line testing of

the interface to guarantee the integrity of the serial

channel before enabling the transmission medium.

Figure 13 shows the basic loopback operation.

output

disabled

CRU

CSU

Figure 13. Loopback Operation

Figure 12. Receiver Timing Half Rate Mode (RATEN Inactive)

Table 9. S2060 Receiver Timing

RBC1

SERIAL DATA IN

RX[9-0]

COMMA

s

r

e

t

e

m

a

r

a

Pn

o

i

t

p

i

r

c

s

e

Dn

i

Mx

a

Ms

t

i

n

Us

n

o

i

t

i

d

n

o

C

T

3

)

0

C

B

R

(

1

C

B

R

e

r

o

f

e

b

d

il

a

v

a

t

a

D0

.

3-

s

n.

1

e

t

o

N

e

e

S

T

4

)

0

C

B

R

(

1

C

B

R

r

e

t

f

a

d

il

a

v

a

t

a

D0

.

2-

s

n

T

R

C

R

T

,

F

C

R

e

m

i

T

ll

a

F

d

n

a

e

s

i

R

0

C

B

R

,

1

C

B

R-

4

.

2s

n.

V

0

.

2

+

o

t

V

8

.

+

d

e

r

u

s

a

e

M

w

e

k

Sw

e

k

S

0

C

B

R

o

t

1

C

B

R5

.

75

.

8s

n.

e

g

d

e

g

n

i

s

i

r

o

t

e

g

d

e

g

n

i

s

i

R

T

R

D

T

,

F

D

e

m

i

T

ll

a

F

d

n

a

e

s

i

R

t

u

p

t

u

O

a

t

a

D-

4

.

2s

n.

V

0

.

2

+

o

t

V

8

.

+

d

e

r

u

s

a

e

M

T

K

C

O

L

)

p

u

t

r

a

t

s

()

G

5

2

.

1

(

e

m

i

t

k

c

o

l

n

o

i

s

i

u

q

c

a

p

u

t

r

a

t

S-

5

.

2s

µ

T

K

C

O

L

)

e

r

i

u

q

c

a

e

r

(

)

G

5

2

.

1

(

e

m

i

T

k

c

o

L

n

o

i

t

i

s

i

u

q

c

A

a

t

a

D

-0

0

1s

n

e

e

s

(

e

y

e

a

t

a

d

t

u

p

n

i

%

0

9

.

)

9

1

e

r

u

g

i

F

-0

5

2s

n.

e

y

e

a

t

a

d

t

u

p

n

i

%

4

2

e

l

c

y

C

y

t

u

D)

0

C

B

R

(

1

C

B

R0

40

6%

T

J

e

c

n

a

r

e

l

o

T

r

e

t

t

i

J

t

u

p

n

I

l

a

t

o

T9

9

5-

s

p.

z

3

.

2

0

8

E

E

E

I

n

i

d

e

i

f

i

c

e

p

s

s

A

T

J

D

e

c

n

a

r

e

l

o

T

r

e

t

t

i

J

t

u

p

n

I

c

i

t

s

i

n

i

m

r

e

t

e

D0

7

3-

s

p.

z

3

.

2

0

8

E

E

E

I

n

i

d

e

i

f

i

c

e

p

s

s

A

1. All AC measurements are made from the reference voltage level of the clock (+1.4 V) to the valid input or output data

levels (+.8 V or +2.0 V).