SP6122 datasheet(15/19 Pages) SIPEX

15 / 19 page

Rev. 7/16/03

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

For the SP6122 example, the schottky

STPS2L25U has VF = 0.5V for IOUT of 4A,

the power loss in the schottky PDIODE =

848mW.

Note that this power dissipation is 2.5 times

greater than the MOSFET. If we assume the

same thermal conductivity as the MOSFET

(according to the data sheets, this is close)

we should get a 40°C rise due to the Schottky

diode alone. It is apparent that due to the

proximity of all the components involved

that the board temperature is higher than

ambient and this temperature rise must be

considered when attempting to protect the

power converter.

Features and Protection

PROGRAMMING THE SP6122 OUTPUT

VOLTAGE

For Applications requiring output other than

1.5V, the 1.25V adjustable version is

recommended. The output voltage can be

programmed through a simple voltage

divider shown in Figure 5. The set point for

the output voltage can be determined by

VOUT =

1.25 (R1 + R2)

Select R1 and R2 in the range from 1k to

100k.

The 1.5V version of SP6122 has built in

voltage divider that presets the output

voltage. Simply connect the VOUT pin to the

power supply output for 1.5V regulation.

Due to the internal voltage divider, the

version of SP6122 sinks 23µA current at

the VOUT pin. Consider this error term if a

resistor voltage divider is used.

SOFT START

The SP6122 has a built-in soft start feature

that automatically limits the inrush currents

to reasonable levels for most power sup-

plies. For our 1.9V example, the inrush cur-

rent on start up is:

IINRUSH = 470µF * 0.5V/ms * 1.9V/1.25V

= 357mA

This extra current must be factored in when

calculating over current margins.

LOCK-UP AND HICCUP MODES

Basically, when the SP6122 sees an over

current fault, the part can react in two ways.

If the FFLAG is not tied to ENABLE, the part

will put the driver into a low impedance state

to the high rail during a fault. The ENABLE

pin must be manually cycled to remove the

fault. This mode is useful when power sup-

ply sequencing and system fault manage-

ment is complex. If the FFLAG pin is tied to

ENABLE, then a ‘hiccup’ time can be de-

signed by adding a capacitor from ENABLE

to ground. The 4µA ENABLE pin charge

current acts as a timer. The driver will be put

into a low impedance state to the high rail for

a certain amount of time.

TOFF = CENABLE* 1.21V/5µA

For CENABLE = 4.7nF, this time equals 1.3ms.

This represents a ‘cool off’ time required for

the power supply to cycle and see if the fault

has been removed. This mode is useful for

short term faults or in single supply systems.

SP6122

VOUT

Pin 3

–

Error

Amplifier

1.25V

–

RIN1

Figure 5: Schematic: Output Voltage Divider Resistors

APPLICATION INFORMATION: Continued

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