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Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

© Copyright 2004 Sipex Corporation

DETAIL DESCRIPTION

Current Mode Control and Slope

Compensation

The SP6652 is designed to use low value ce-

ramic capacitors and low value inductors, to

reduce the converter’s volume and cost in por-

table devices Current mode PWM control was,

therefore, chosen for the ease of compensation

when using ceramic output capacitors and better

transient line rejection, which is important in

battery powered applications. Current mode

control spreads the two poles of the output

power train filter far apart so that the modulator

gain crosses over at

-20dB/decade instead of

the usual -40dB/decade. The external compen-

sation network is, simply, a series RC connected

between ground and the output of the internal

transconductance error amplifier.

It is well known that an unconditional instability

exists for any fixed frequency current-mode

converter operating above 50% duty cycle. A

simple, constant-slope compensation is chosen

to achieve stability under these conditions. The

most common high duty cycle application is a

Li-Ion battery powered regulator with a 3.3V

output (D

≥ 90%). Since the current loop is

critically damped when the compensation slope

pensation chosen is, therefore:

-702mA/

µs

for RPMOS = 0.20

Ω

The inductor current is sensed as a voltage

across the PMOS charging switch and the NMOS

synchronous rectifier (see BLOCK DIAGRAM)

During inductor current charge, V(PVIN)-V(LX)

represents the charging current ramp times the

resistance of the PMOS charging switch. To

keep the effective current slope compensation

constant (remembering current is being com-

pensated, not voltage) the voltage slope must be

slope compensation voltage is internally gener-

ated with a bias current that is also proportional

Over Current Protection

In steady state closed loop operation the voltage

at the COMP pin controls the duty cycle. Due to

the current mode control and the slope compen-

sation, this voltage will be:

The COMP node will be clamped when the its

the output of the translator. The correct value of

clamp voltage is, therefore:

V(BLIM) = IL(MAX)* RPMOS + MCV *tON

of current limit approximately constant over

process and temperature variations, while the

cuit that senses the amplitude of the slope com-

even if the COMP node is at 0V, since the peak

current comparator is reset at the end of a charge

cycle and is held low during a blanking time

after the start of the next charge cycle. This is

necessary to swamp the transients in the induc-

tor current ramp around switching times. The

cient for the COMP node to keep control of the

current when the output voltage is low. The

inductor current tends to rise until the energy

loss from the discharge resistances are equal to