6

Date:5/25/04

SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator

© Copyright 2004 Sipex Corporation

the energy gained during the charge phase. For

this reason, the clock frequency is cut in half

when the feedback pin is below 0.3V, effec-

tively reducing the minimum duty cycle in half.

Above V(FB)=0.3V the clock frequency is nor-

mal (see TYPICAL OPERATIONG CHAR-

ACTERISTICS: Inductor current vs. VOUT)

PFM Control for Light Loads

light load conditions the SP6652 will transition

to a PFM regulation mode. In this mode of

operation, V(FB) is compared to the reference

voltage plus 7.5mV, nominally (see BLOCK

DIAGRAM). This sets the regulation point 1%

higher than the PWM regulation voltage to

prevent bouncing between modes at loading

conditions near threshold.

point the voltage loop comparator issues a com-

mand to turn on the PMOS switch to the output

stage logic. The current sensing comparator

compares the voltage across that switch to a

reference set up by a biased replica of the PMOS

switch, to set the peak PFM inductor current

(nominally 300 mA). This comparator stops the

charging cycle and initiates the discharge through

the synchronous NMOS rectifier.

Any new charging cycles are inhibited until a

third comparator, the under-current compara-

tor, which is setup to detect the instant when the

enables the voltage loop. This keeps the PFM

mode in discontinuous conduction mode (DCM).

A timer disables both the Current Loop and

Trough Current comparators 7

µs after entering

DCM, to save supply current under very light

load conditions. The normal light load supply

current is, nominally, 135

µA whereas the very

light load supply current is 60

µA.

DETAIL DESCRIPTION: Contunued

Automatic Mode Selection

If the MODE pin is connected to SVIN, the part

will be forced into a PWM-only regulation mode.

selection circuitry decides whether the con-

verter should be in PWM or PFM mode, depend-

ing on the load. Light loads call for the PFM

loop, which is forced into DCM as well. Me-

dium to heavy loads activate the PWM loop.

Starting from a PWM state, the Peak and Trough

Current Detector window comparator monitors

the peak inductor current during charge and the

trough inductor current during discharge. Both

the peak and trough are monitored because the

ripple current varies considerably across the

application spectrum. The lossless inductor cur-

rent ripple is:

nominally).

If the peak inductor current is below 100mA or

the trough reaches 0mA (or less) during one

cycle, then the current is defined as low enough

for PFM mode. This has to happen during 32

consecutive clock cycles before the output sig-

nal goes high and switches modes. This delay is

to avoid prematurely switching into PFM mode

during a negative load transient.

Once in PFM mode, the regulated output volt-

age will be 1% higher than in PWM and con-

tinue regulating there, as described in the PFM

Control For Light Loads section. When the load

increases past the point where the PFM mode

can regulate while remaining in DCM (which is

l 1/2 of the peak inductor current in PFM, or 1/

2*300mA=150mA), the output voltage will start

dropping. When it falls 1% below the reference

voltage, that is 2% below the PFM regulation

point, the PWM Mode Comparator will switch

and set the Mode Control latch to PWM mode.