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PI6CDBL401B

Rev.C

03/23/16

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PI6CDBL401B

4-Output Low Power PCIE GEN1-2-3 Buffer

Byte 0 Name

Control Function

Type

0

1

Default

7

Reserved

1

6

OE3

Output Enable

RW

Low

Enabled

1

5

OE2

Output Enable

RW

Low

Enabled

1

4

Reserved

1

3

OE1

Output Enable

RW

Low

Enabled

1

2

Reserved

1

1

OE0

Output Enable

RW

Low

Enabled

1

0

Reserved

1

1. A low on these bits will overide the OE# pin and force the differential output Low.

SMBus Table: DIF Slew Rate Control Register

Byte 2 Name

Control Function

Type

0

1

Default

7

Reserved

1

6

SLEWRATE-

SEL DIF3

Slew Rate Selection

RW

2 V/ns

3 V/ns

1

5

SLEWRATE-

SEL DIF2

Slew Rate Selection

RW

2 V/ns

3 V/ns

1

4

Reserved

1

3

SLEWRATE-

SEL DIF1

Slew Rate Selection

RW

2 V/ns

3 V/ns

1

2

Reserved

1

SMBus Table: PLL Operating Mode and Output Amplitude Control Register

Byte 1 Name

Control Function

Type

0

1

Default

7

PLL-

MODERB1

PLL Mode Readback Bit 1

R

See PLL Operating Mode Table

Latch

6

PLL-

MODERB0

PLL Mode Readback Bit 0

R

Latch

5

PLLMODE_

SWCNTRL

Enable SW control of PLL Mode

RW

Values in

B1[7:6]

set PLL Mode

Values in B1[4:3]

set PLL Mode

0

4

PLLMODE1

PLL Mode Control Bit 1

See PLL Operating Mode Table

0

3

PLLMODE0

PLL Mode Control Bit 0

0

2

Reserved

1

1

AMPLITUDE

1

Controls Output Amplitude

RW

00 = 0.6V

01 = 0.7V

1

0

AMPLITUDE

0

RW

10= 0.8V

11 = 0.9V

0

1. B1[5] must be set to a 1 for these bits to have any effect on the part.

16-0064