ADC0833 datasheet(12/20 Pages) NSC

12 / 20 page

Functional Description (Continued)

40 THE ANALOG INPUTS

The most important feature of these converters is that they

can be located right at the analog signal source and through

just a few wires can communicate with a controlling proces-

sor with a highly noise immune serial bit stream This in itself

greatly minimizes circuitry to maintain analog signal accura-

cy which otherwise is most susceptible to noise pickup

However a few words are in order with regard to the analog

inputs should the inputs be noisy to begin with or possibly

riding on a large common-mode voltage

The differential input of these converters actually reduces

the effects of common-mode input noise a signal common

to both selected ‘‘a’’ and ‘‘b’’ inputs for a conversion (60

Hz is most typical) The time interval between sampling the

‘‘a’’ input and then the ‘‘b’’ input is

of a clock period

The change in the common-mode voltage during this short

time interval can cause conversion errors For a sinusoidal

common-mode signal this error is

Verror(max) e VPEAK(2qfCM)

fCLK

where fCM is the frequency of the common-mode signal

VPEAK is its peak voltage value

and fCLK is the AD clock frequency

For a 60 Hz common-mode signal to generate a

LSB

error (

5 mV) with the converter running at 250 kHz its

peak value would have to be 663V which would be larger

than allowed as it exceeds the maximum analog input limits

Due to the sampling nature of the analog inputs short spikes

of current enter the ‘‘a’’ input and exit the ‘‘b’’ input at the

clock edges during the actual conversion These currents

decay rapidly and do not cause errors as the internal com-

parator is strobed at the end of a clock period Bypass ca-

pacitors at the inputs will average these currents and cause

an effective DC current to flow through the output resist-

ance of the analog signal source Bypass capacitors should

not be used if the source resistance is greater than 1 kX

This source resistance limitation is important with regard to

the DC leakage currents of input multiplexer as well The

worst-case leakage current of g 1 mA over temperature will

createa1mV inut error witha1kX source resistance An

op amp RC active low pass filter can provide both imped-

ance buffering and noise filtering should a high impedance

signal source be required

50 OPTIONAL ADJUSTMENTS

51 Zero Error

The zero of the AD does not require adjustment If the

minimum analog input voltage value VIN(MIN) is not ground

a zero offset can be done The converter can be made to

output 0000 0000 digital code for this minimum input voltage

by biasing any VIN (b) input at this VIN(MIN) value This

utilizes the differential mode operation of the AD

The zero error of the AD converter relates to the location

of the first riser of the transfer function and can be mea-

sured by grounding the VIN(b) input and applying a small

magnitude positive voltage to the VIN(a) input Zero error is

the difference between the actual DC input voltage which

is necessary to just cause an output digital code transition

from 0000 0000 to 0000 0001 and the ideal

LSB value

(

LSBe98 mV for VREF 2e2500 VDC)

52 Full-Scale

The full-scale adjustment can be made by applying a differ-

ential input voltage which is 1

LSB down from the desired

analog full-scale voltage range and then adjusting the mag-

nitude of the VREF input or VCC for a digital output code

which is just changing from 1111 1110 to 1111 1111

53 Adjusting for an Arbitrary Analog Input Voltage

Range

If the analog zero voltage of the AD is shifted away from

ground (for example to accommodate an analog input sig-

nal which does not go to ground) this new zero reference

should be properly adjusted first A VIN(a) voltage which

equals this desired zero reference plus

LSB (where the

LSB is calculated for the desired analog span

using

1 LSBeanalog span256) is applied to selected ‘‘a’’ input

and the zero reference voltage at the corresponding ‘‘b’’

input should then be adjusted to just obtain the 00HEX to

01HEX code transition

The full-scale adjustment should be made with the proper

VIn(b) voltage applied by forcing a voltage to the VIN(a)

input which is given by

VIN (a)fsadj e VMAX b 15

(VMAX b VMIN)

256

(

where

VMAXe the high end of the analog input range

and

VMINe the low end (the offset zero) of the analog

range

(Both are ground referenced)

The VREF 2 voltage is then adjusted to provide a code

change from FEHEX to FFHEX This completes the adjust-

ment procedure

60 POWER SUPPLY

A unique feature of the ADC0833 is the inclusion of a 7V

zener diode connected from the Va terminal to ground

which also connects to the VCC terminal (which is the actual

converter supply) through a silicon diode as shown in

Fig-

ure 3

TLH5607 – 8

FIGURE 3 An On-Chip Shunt Regulator Diode

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