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ADC08351 Datasheet(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # ADC08351
Description  8-Bit, 42 MSPS, 40 mW A/D Converter
PDF  15 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC08351 Datasheet(HTML) 5 Page - National Semiconductor (TI)

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Converter Electrical Characteristics (Continued)
The following specifications apply for V
A =VD = +3.0 VDC,VREF = 2.4V, VIN = 1.63 VP-P, OE = 0V, CL = 20 pF,
f
CLK = 42 MHz, 50% duty cycle, unless otherwise specified.
Boldface limits apply for T
A =TMIN to TMAX: all other limits TA = 25˚C (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
(Limits)
Digital Output Characteristics
I
OH
High Level Output Current
V
D = 2.7V, VOH =VD −0.5V
−1.1
mA (min)
I
OL
Low Level Output Current
V
D = 2.7V, OE = DGND, VOL = 0.4V
1.8
mA (min)
V
OH
High Level Output Voltage
V
D = 2.7V, IOH = −360 µA
2.65
V
V
OL
Low Level Output Voltage
V
D = 2.7V, IOL = 1.6 mA
0.2
V
I
OZH,
I
OZL
TRI-STATE Output Current
OE = V
D = 3.3V, VOH = 3.3V or VOL =0V
±10
µA
AC Electrical Characteristics
f
C1
Maximum Conversion Rate
42
MHz (min)
f
C2
Minimum Conversion Rate
2
MHz
t
OD
Output Delay
CLK High to Data Valid
14
19
ns (max)
Pipline Delay (Latency)
2.5
Clock
Cycles
t
DS
Sampling (Aperture) Delay
CLK Low to Acquisition of Data
2
ns
t
OH
Output Hold Time
CLK High to Data Invalid
9
ns
t
EN
OE Low to Data Valid
Loaded as in
Figure 2
14
ns
t
DIS
OE High to High Z State
Loaded as in
Figure 2
10
ns
ENOB
Effective Number of Bits
f
CLK = 30 MHz, fIN = 1 MHz
7.2
Bits
f
CLK = 42 MHz, fIN = 4.4 MHz
7.2
Bits
f
CLK = 42 MHz, fIN = 21 MHz
6.8
6.1
Bits (min)
SINAD
Signal-to-Noise & Distortion
f
CLK = 30 MHz, fIN = 1 MHz
45
dB
f
CLK = 42 MHz, fIN = 4.4 MHz
45
dB
f
CLK = 42 MHz, fIN = 21 MHz
43
38.5
dB (min)
SNR
Signal-to-Noise Ratio
f
CLK = 30 MHz, fIN = 1 MHz
44
dB
f
CLK = 42 MHz, fIN = 4.4 MHz
45
dB
f
CLK = 42 MHz, fIN = 21 MHz
44
41
dB (min)
THD
Total Harmonic Distortion
f
CLK = 30 MHz, fIN = 1 MHz
−57
dB
f
CLK = 42 MHz, fIN = 4.4 MHz
−51
dB
f
CLK = 42 MHz, fIN = 21 MHz
−46
−41
dB (min)
SFDR
Spurious Free Dynamic Range
f
CLK = 30 MHz, fIN = 1 MHz
57
dB
f
CLK = 42 MHz, fIN = 4.4 MHz
54
dB
f
CLK = 42 MHz, fIN = 21 MHz
49
41
dB (min)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-
fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DGND, or greater than VA or VD), the current at that pin should
be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (
θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. For the 20-pin
TSSOP,
θJA is 135˚C/W, so PDMAX = 926 mW at 25˚C and 481 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this
device under normal operation will typically be about 68 mW (40 mW quiescent power + 23 mW reference ladder power+5mWdue to 1 TTL loan on each digital
output). The values for maximum power dissipation listed above will be reached only when the ADC08351 is operated in a severe fault condition (e.g., when input
or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k
Ω resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: All inputs are protected as shown below. Input voltage magnitudes up to 500 mV above the supply voltage or 500 mV below GND will not damage this device.
However, errors in the A/D conversion can occur if the input goes above VA or below AGND by more than 300 mV. As an example, if VA is 3.0 VDC, the full-scale
input voltage must be
≤3.3 VDC to ensure accurate conversions.
www.national.com
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