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PI6LC4820 Rev D

11/13/13

PI6LC4820

Input Mux Selection

IN_SEL

Input

0

Select Crystal Input (Pins 2, 3)

1

Select IN+, IN- Differential Input (Pins 46, 47)

NC

Select IN_SE LVCMOS Input (pin 48)

PLL Bypass Control Function

PLL_BYPS

PLL operation

0

PLL enabled

1

PLL bypassed

NC

PLL enabled for Banks A, B; Bank C is driven directly by the output of the input mux.

Pin Number Pin Name

Type

Description

32,

33

QA1-,

QA1+

Output (Differential)

Bank A LVDS/LVPECL selectable output. Controlled by QA_Mode0 pin

34,

35

QA0-,

QA0+

Output (Differential)

Bank A LVDS/LVPECL selectable output. Controlled by QA_Mode0 pin

36

Power

37

Power

38,

39

QB0-,

QB0+

Output (Differential)

Bank B LVDS/LVPECL selectable output. Controlled by QB_Mode pin

40,

41

QB1-,

QB1+

Output (Differential)

Bank B LVDS/LVPECL selectable output. Controlled by QB_Mode pin

42,

43

QB2-,

QB2+

Output (Differential)

Bank B LVDS/LVPECL selectable output. Controlled by QB_Mode pin

44,

45

QA_Mode0,

QB_Mode

Input (LVCMOS)

Out mode control pins select LVPECL, LVDS mode. If left floating,

outputs are tri-stated

46

IN-

Input (Differential)

Frequency input pin, differential (accepts: LVDS, LVPECL, HCSL)

47

IN+

Input (Differential)

Frequency input pin, differential (accepts: LVDS, LVPECL, HCSL)

48

IN_SE

Input

Frequency input pin, Single Ended

Input Divider Control Table

FS0

Divider Ratio

0

1

1

5

Pin Description (Continued..)

13-0167